Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45812191

1

T1

241

T2

162

T3

6

full_word

45270124

1

T1

329

T2

295

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91082005	1			T1	570		T2	457		T3	12
auto[TlIntgErrCmd]	112	1			T138	3		T139	9		T140	3
auto[TlIntgErrData]	95	1			T138	4		T139	6		T140	4
auto[TlIntgErrBoth]	103	1			T138	3		T139	5		T140	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50421451

1

T1

223

T2

177

T3

5

auto[1]

40660864

1

T1

347

T2

280

T3

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	30080350	1			T1	120		T2	92		T3	3
auto[TlIntgErrNone]	partial	auto[1]	15731554	1			T1	121		T2	70		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	20340957	1			T1	103		T2	85		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	24929144	1			T1	226		T2	210		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T138	1		T139	3		T140	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T138	2		T139	5		T140	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T194	1		T195	2		T196	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T139	1		T197	1		T198	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T138	3		T139	2		T140	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T138	1		T139	2		T140	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T139	2		T199	1		T198	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T193	1		T189	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T138	3		T139	1		T140	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T139	4		T140	2		T192	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T193	1		T192	1		T198	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T193	1		T188	1		T199	1