Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	596020898	54901	0	0
RunThenComplete_M	596020898	671970	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596020898	54901	0	0
T1	5111	3	0	0
T2	8662	3	0	0
T3	1316	0	0	0
T4	0	19	0	0
T7	0	14	0	0
T8	0	9	0	0
T10	2544	0	0	0
T17	7433	3	0	0
T44	0	73	0	0
T46	770	0	0	0
T47	1595	0	0	0
T48	3326	0	0	0
T49	10758	3	0	0
T50	2893	0	0	0
T51	0	3	0	0
T52	0	3	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596020898	671970	0	0
T1	5111	10	0	0
T2	8662	10	0	0
T3	1316	0	0	0
T7	0	42	0	0
T8	0	27	0	0
T9	0	1	0	0
T10	2544	0	0	0
T17	7433	11	0	0
T44	0	74	0	0
T46	770	0	0	0
T47	1595	0	0	0
T48	3326	0	0	0
T49	10758	11	0	0
T50	2893	0	0	0
T51	0	10	0	0
T52	0	10	0	0