Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597449271	56072786	0	0
DepthKnown_A	597449271	597232198	0	0
RvalidKnown_A	597449271	597232198	0	0
WreadyKnown_A	597449271	597232198	0	0
gen_passthru_fifo.paramCheckPass	880	880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	56072786	0	0
T1	5111	444	0	0
T2	8662	354	0	0
T3	1316	12	0	0
T10	2544	88	0	0
T17	7433	525	0	0
T46	770	11	0	0
T47	1595	86	0	0
T48	3326	217	0	0
T49	10758	619	0	0
T50	2893	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	597232198	0	0
T1	5111	5061	0	0
T2	8662	8577	0	0
T3	1316	1242	0	0
T10	2544	2407	0	0
T17	7433	7344	0	0
T46	770	695	0	0
T47	1595	1526	0	0
T48	3326	3230	0	0
T49	10758	10708	0	0
T50	2893	2823	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	597232198	0	0
T1	5111	5061	0	0
T2	8662	8577	0	0
T3	1316	1242	0	0
T10	2544	2407	0	0
T17	7433	7344	0	0
T46	770	695	0	0
T47	1595	1526	0	0
T48	3326	3230	0	0
T49	10758	10708	0	0
T50	2893	2823	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	597232198	0	0
T1	5111	5061	0	0
T2	8662	8577	0	0
T3	1316	1242	0	0
T10	2544	2407	0	0
T17	7433	7344	0	0
T46	770	695	0	0
T47	1595	1526	0	0
T48	3326	3230	0	0
T49	10758	10708	0	0
T50	2893	2823	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597449271	115405814	0	0
DepthKnown_A	597449271	597232198	0	0
RvalidKnown_A	597449271	597232198	0	0
WreadyKnown_A	597449271	597232198	0	0
gen_passthru_fifo.paramCheckPass	880	880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	115405814	0	0
T1	5111	444	0	0
T2	8662	354	0	0
T3	1316	54	0	0
T10	2544	403	0	0
T17	7433	525	0	0
T46	770	11	0	0
T47	1595	86	0	0
T48	3326	217	0	0
T49	10758	619	0	0
T50	2893	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	597232198	0	0
T1	5111	5061	0	0
T2	8662	8577	0	0
T3	1316	1242	0	0
T10	2544	2407	0	0
T17	7433	7344	0	0
T46	770	695	0	0
T47	1595	1526	0	0
T48	3326	3230	0	0
T49	10758	10708	0	0
T50	2893	2823	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	597232198	0	0
T1	5111	5061	0	0
T2	8662	8577	0	0
T3	1316	1242	0	0
T10	2544	2407	0	0
T17	7433	7344	0	0
T46	770	695	0	0
T47	1595	1526	0	0
T48	3326	3230	0	0
T49	10758	10708	0	0
T50	2893	2823	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	597232198	0	0
T1	5111	5061	0	0
T2	8662	8577	0	0
T3	1316	1242	0	0
T10	2544	2407	0	0
T17	7433	7344	0	0
T46	770	695	0	0
T47	1595	1526	0	0
T48	3326	3230	0	0
T49	10758	10708	0	0
T50	2893	2823	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0