Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	597449271	13959	0	0
entropy_period_rd_A	597449271	1470	0	0
intr_enable_rd_A	597449271	2086	0	0
prefix_0_rd_A	597449271	1608	0	0
prefix_10_rd_A	597449271	1561	0	0
prefix_1_rd_A	597449271	1600	0	0
prefix_2_rd_A	597449271	1534	0	0
prefix_3_rd_A	597449271	1572	0	0
prefix_4_rd_A	597449271	1583	0	0
prefix_5_rd_A	597449271	1505	0	0
prefix_6_rd_A	597449271	1491	0	0
prefix_7_rd_A	597449271	1555	0	0
prefix_8_rd_A	597449271	1564	0	0
prefix_9_rd_A	597449271	1584	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	13959	0	0
T13	307309	0	0	0
T16	0	2714	0	0
T24	21228	0	0	0
T55	143008	0	0	0
T65	110108	579	0	0
T66	0	2938	0	0
T136	195263	0	0	0
T138	0	2	0	0
T139	0	2	0	0
T144	0	4391	0	0
T145	0	85	0	0
T146	0	6	0	0
T147	0	188	0	0
T149	0	143	0	0
T150	107172	0	0	0
T151	3045	0	0	0
T152	24335	0	0	0
T153	180291	0	0	0
T154	64635	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1470	0	0
T114	2884	10	0	0
T115	4567	11	0	0
T119	4507	3	0	0
T148	4826	8	0	0
T167	10927	23	0	0
T168	1739	7	0	0
T169	6111	15	0	0
T170	2747	6	0	0
T171	10317	24	0	0
T172	63383	55	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	2086	0	0
T114	2884	10	0	0
T115	4567	14	0	0
T119	4507	14	0	0
T148	4826	5	0	0
T167	10927	34	0	0
T168	1739	4	0	0
T169	6111	25	0	0
T171	10317	17	0	0
T172	63383	118	0	0
T173	1225	24	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1608	0	0
T115	4567	4	0	0
T119	4507	12	0	0
T148	4826	1	0	0
T167	10927	64	0	0
T168	1739	3	0	0
T169	6111	17	0	0
T170	2747	2	0	0
T171	10317	15	0	0
T172	63383	134	0	0
T174	3098	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1561	0	0
T114	2884	2	0	0
T115	4567	6	0	0
T119	4507	19	0	0
T148	4826	4	0	0
T167	10927	47	0	0
T168	1739	9	0	0
T169	6111	16	0	0
T170	2747	9	0	0
T171	10317	35	0	0
T172	63383	110	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1600	0	0
T114	2884	7	0	0
T115	4567	5	0	0
T119	4507	16	0	0
T148	4826	8	0	0
T167	10927	24	0	0
T168	1739	2	0	0
T169	6111	11	0	0
T170	2747	4	0	0
T171	10317	20	0	0
T172	63383	151	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1534	0	0
T114	2884	6	0	0
T115	4567	20	0	0
T119	4507	9	0	0
T148	4826	6	0	0
T167	10927	24	0	0
T168	1739	6	0	0
T169	6111	3	0	0
T171	10317	16	0	0
T172	63383	109	0	0
T174	3098	15	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1572	0	0
T114	2884	6	0	0
T115	4567	10	0	0
T119	4507	11	0	0
T148	4826	6	0	0
T167	10927	43	0	0
T168	1739	2	0	0
T169	6111	26	0	0
T171	10317	30	0	0
T172	63383	129	0	0
T174	3098	12	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1583	0	0
T114	2884	3	0	0
T115	4567	9	0	0
T119	4507	7	0	0
T167	10927	80	0	0
T168	1739	3	0	0
T169	6111	25	0	0
T170	2747	2	0	0
T171	10317	29	0	0
T172	63383	172	0	0
T174	3098	6	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1505	0	0
T114	2884	9	0	0
T115	4567	12	0	0
T119	4507	9	0	0
T148	4826	1	0	0
T167	10927	70	0	0
T168	1739	5	0	0
T169	6111	11	0	0
T170	2747	9	0	0
T171	10317	40	0	0
T172	63383	125	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1491	0	0
T114	2884	1	0	0
T115	4567	8	0	0
T119	4507	3	0	0
T148	4826	5	0	0
T167	10927	36	0	0
T168	1739	9	0	0
T169	6111	14	0	0
T170	2747	8	0	0
T171	10317	10	0	0
T172	63383	137	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1555	0	0
T114	2884	8	0	0
T115	4567	14	0	0
T119	4507	8	0	0
T148	4826	8	0	0
T167	10927	14	0	0
T168	1739	2	0	0
T169	6111	29	0	0
T170	2747	1	0	0
T171	10317	13	0	0
T172	63383	155	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1564	0	0
T114	2884	5	0	0
T115	4567	9	0	0
T119	4507	4	0	0
T167	10927	16	0	0
T168	1739	5	0	0
T169	6111	3	0	0
T170	2747	9	0	0
T171	10317	23	0	0
T172	63383	148	0	0
T174	3098	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597449271	1584	0	0
T114	2884	6	0	0
T115	4567	14	0	0
T119	4507	15	0	0
T167	10927	21	0	0
T168	1739	6	0	0
T169	6111	8	0	0
T171	10317	11	0	0
T172	63383	155	0	0
T174	3098	3	0	0
T175	125151	274	0	0