Unified Coverage Report :: Module :: prim_generic_flop_en

Module : prim_generic_flop_en

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_t01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_inner_domain_regs.u_prim_flop_tab01

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_flop_en

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_flop_en

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.u_prim_flop_t01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	32	4	4	100.00

27                        end else begin : gen_en_no_sec_buf
28         1/1              assign en = en_i;
           Tests:       T1 T2 T3 
29                        end
30                      
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
34         1/1              end else if (en) begin
           Tests:       T1 T2 T3 
35         1/1                q_o <= d_i;
           Tests:       T1 T2 T17 
36                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.gen_inner_domain_regs.u_prim_flop_tab01.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               q_o <= ResetValue;
                 ==>
34             end else if (en) begin
                        -2-  
35               q_o <= d_i;
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3