Unified Coverage Report :: Group :: kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg

Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
AppKeymgr_cg_(1)	100.00	1	100	1	64	64
AppLc_cg_(1)	100.00	1	100	1	64	64
AppRom_cg_(1)	100.00	1	100	1	64	64

---

Group Instance : AppKeymgr_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance AppKeymgr_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance AppKeymgr_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sw_configured_hash_mode	3	0	3	100.00	100	1	1	0

---

Group Instance : AppLc_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance AppLc_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance AppLc_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sw_configured_hash_mode	3	0	3	100.00	100	1	1	0

---

Group Instance : AppRom_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance AppRom_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance AppRom_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sw_configured_hash_mode	3	0	3	100.00	100	1	1	0

Summary for Variable sw_configured_hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for sw_configured_hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	1098	1			T4	9		T10	1		T14	3
shake	1096	1			T9	2		T4	3		T5	11
sha3	1184	1			T9	1		T4	12		T14	1

Summary for Variable sw_configured_hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for sw_configured_hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	543	1			T4	1		T10	1		T5	8
shake	570	1			T4	6		T10	1		T14	2
sha3	571	1			T9	1		T4	3		T5	2

Summary for Variable sw_configured_hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for sw_configured_hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	554	1			T4	3		T10	1		T5	6
shake	548	1			T4	4		T5	1		T15	3
sha3	525	1			T4	1		T10	3		T14	1