Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47529984

1

T1

16

T2

13

T3

8

full_word

46002093

1

T1

2

T2

14

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	93531847	1			T1	18		T2	27		T3	16
auto[TlIntgErrCmd]	86	1			T125	5		T126	5		T127	2
auto[TlIntgErrData]	67	1			T125	2		T126	4		T127	4
auto[TlIntgErrBoth]	77	1			T125	3		T126	1		T127	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51912382

1

T1

1

T2

9

T3

5

auto[1]

41619695

1

T1

17

T2

18

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	31729140	1			T2	6		T3	2		T11	240
auto[TlIntgErrNone]	partial	auto[1]	15800638	1			T1	16		T2	7		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	20183148	1			T1	1		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	25818921	1			T1	1		T2	11		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	25	1			T125	1		T126	1		T171	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T125	3		T126	3		T127	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T126	1		T171	2		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T125	1		T174	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	29	1			T126	3		T127	2		T171	1
auto[TlIntgErrData]	partial	auto[1]	31	1			T125	2		T126	1		T127	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T174	1		T173	1		T179	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T127	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	26	1			T125	1		T127	2		T171	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T125	1		T126	1		T127	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T171	1		T180	1		T174	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T125	1		T175	1		T173	1