Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	611217475	15651	0	0
entropy_period_rd_A	611217475	2521	0	0
intr_enable_rd_A	611217475	3300	0	0
prefix_0_rd_A	611217475	2933	0	0
prefix_10_rd_A	611217475	2765	0	0
prefix_1_rd_A	611217475	2980	0	0
prefix_2_rd_A	611217475	2988	0	0
prefix_3_rd_A	611217475	2869	0	0
prefix_4_rd_A	611217475	2953	0	0
prefix_5_rd_A	611217475	2921	0	0
prefix_6_rd_A	611217475	2937	0	0
prefix_7_rd_A	611217475	2855	0	0
prefix_8_rd_A	611217475	3012	0	0
prefix_9_rd_A	611217475	2803	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	15651	0	0
T17	60916	0	0	0
T28	0	4008	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	2117	0	0
T52	0	2765	0	0
T74	955	0	0	0
T83	0	1436	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T122	1377	0	0	0
T125	0	1	0	0
T131	0	2178	0	0
T132	0	4	0	0
T133	0	217	0	0
T134	0	153	0	0
T135	0	118	0	0
T137	359610	0	0	0
T138	26328	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2521	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	48	0	0
T74	955	0	0	0
T83	0	18	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	1	0	0
T107	0	22	0	0
T108	0	27	0	0
T122	1377	0	0	0
T129	0	13	0	0
T132	0	9	0	0
T133	0	2	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	3	0	0
T153	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	3300	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	43	0	0
T74	955	0	0	0
T83	0	27	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T107	0	34	0	0
T108	0	27	0	0
T122	1377	0	0	0
T129	0	7	0	0
T130	0	9	0	0
T132	0	4	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	24	0	0
T153	0	4	0	0
T154	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2933	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	49	0	0
T74	955	0	0	0
T83	0	27	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	7	0	0
T107	0	6	0	0
T108	0	16	0	0
T122	1377	0	0	0
T127	0	54	0	0
T129	0	2	0	0
T132	0	13	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	6	0	0
T153	0	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2765	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	69	0	0
T74	955	0	0	0
T83	0	17	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	7	0	0
T107	0	7	0	0
T108	0	35	0	0
T122	1377	0	0	0
T127	0	50	0	0
T129	0	5	0	0
T132	0	3	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	7	0	0
T153	0	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2980	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	41	0	0
T74	955	0	0	0
T83	0	36	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	6	0	0
T108	0	26	0	0
T122	1377	0	0	0
T127	0	50	0	0
T129	0	12	0	0
T132	0	7	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	9	0	0
T153	0	2	0	0
T155	0	111	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2988	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	57	0	0
T74	955	0	0	0
T83	0	14	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T107	0	32	0	0
T108	0	45	0	0
T122	1377	0	0	0
T127	0	37	0	0
T129	0	1	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T153	0	13	0	0
T155	0	129	0	0
T156	0	10	0	0
T157	0	462	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2869	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	35	0	0
T74	955	0	0	0
T83	0	14	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	3	0	0
T107	0	8	0	0
T108	0	32	0	0
T122	1377	0	0	0
T127	0	32	0	0
T129	0	3	0	0
T132	0	12	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	10	0	0
T153	0	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2953	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	44	0	0
T74	955	0	0	0
T83	0	14	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	8	0	0
T108	0	19	0	0
T122	1377	0	0	0
T127	0	53	0	0
T129	0	13	0	0
T132	0	7	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	19	0	0
T153	0	7	0	0
T155	0	141	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2921	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	42	0	0
T74	955	0	0	0
T83	0	15	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T107	0	23	0	0
T108	0	28	0	0
T122	1377	0	0	0
T127	0	47	0	0
T129	0	11	0	0
T132	0	11	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	19	0	0
T153	0	4	0	0
T155	0	111	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2937	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	42	0	0
T74	955	0	0	0
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T102	25286	0	0	0
T103	384960	0	0	0
T105	0	5	0	0
T107	0	14	0	0
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T122	1377	0	0	0
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T129	0	5	0	0
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T137	359610	0	0	0
T138	26328	0	0	0
T152	0	4	0	0
T153	0	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2855	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	37	0	0
T74	955	0	0	0
T83	0	29	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	6	0	0
T107	0	2	0	0
T108	0	22	0	0
T122	1377	0	0	0
T127	0	33	0	0
T129	0	6	0	0
T132	0	5	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	7	0	0
T153	0	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	3012	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	47	0	0
T74	955	0	0	0
T83	0	39	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	8	0	0
T107	0	19	0	0
T108	0	26	0	0
T122	1377	0	0	0
T129	0	11	0	0
T132	0	8	0	0
T133	0	5	0	0
T137	359610	0	0	0
T138	26328	0	0	0
T152	0	12	0	0
T153	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611217475	2803	0	0
T17	60916	0	0	0
T43	1922	0	0	0
T49	106034	0	0	0
T51	512668	41	0	0
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T83	0	29	0	0
T102	25286	0	0	0
T103	384960	0	0	0
T105	0	8	0	0
T107	0	12	0	0
T108	0	26	0	0
T122	1377	0	0	0
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