Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48473602

1

T1

4471

T2

5025

T3

8140

full_word

47607864

1

T1

21223

T2

5846

T3

7411

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	96081156	1			T1	25694		T2	10871		T3	15551
auto[TlIntgErrCmd]	95	1			T105	4		T106	9		T107	9
auto[TlIntgErrData]	99	1			T105	7		T106	4		T107	6
auto[TlIntgErrBoth]	116	1			T105	9		T106	7		T107	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53054532

1

T1

14817

T2

6245

T3

8279

auto[1]

43026934

1

T1

10877

T2

4626

T3

7272

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	31820829	1			T1	2527		T2	2689		T3	4485
auto[TlIntgErrNone]	partial	auto[1]	16652488	1			T1	1944		T2	2336		T3	3655
auto[TlIntgErrNone]	full_word	auto[0]	21233565	1			T1	12290		T2	3556		T3	3794
auto[TlIntgErrNone]	full_word	auto[1]	26374274	1			T1	8933		T2	2290		T3	3617
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T105	1		T106	3		T107	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T105	3		T106	5		T107	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T149	1		T150	1		T151	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T106	1		T107	1		T145	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T105	3		T106	4		T107	2
auto[TlIntgErrData]	partial	auto[1]	35	1			T105	3		T107	4		T152	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T148	1		T153	2		T154	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T105	1		T145	1		T149	2
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T105	4		T106	4		T107	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T105	5		T106	2		T107	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T106	1		T148	1		T155	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T107	1		T145	1		-	-