Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	646966534	58367	0	0
RunThenComplete_M	646966534	721176	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646966534	58367	0	0
T1	159591	157	0	0
T2	85468	105	0	0
T3	105629	137	0	0
T4	1606	0	0	0
T7	39374	4	0	0
T9	27812	4	0	0
T10	189613	22	0	0
T12	0	14	0	0
T22	0	15	0	0
T29	4436	3	0	0
T30	5572	3	0	0
T43	1805	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	646966534	721176	0	0
T1	159591	395	0	0
T2	85468	106	0	0
T3	105629	138	0	0
T4	1606	0	0	0
T7	39374	12	0	0
T9	27812	17	0	0
T10	189613	121	0	0
T11	0	1	0	0
T12	0	82	0	0
T29	4436	11	0	0
T30	5572	11	0	0
T43	1805	0	0	0