Unified Coverage Report :: Module Instance :: tb.dut.u_tlul_adapter_msgfifo.u

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T3 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T3 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T29,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	646966534	49971347	0	0
DepthKnown_A	646966534	646807694	0	0
RvalidKnown_A	646966534	646807694	0	0
WreadyKnown_A	646966534	646807694	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	646966534	49971347	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	646966534	49971347
T1	159591	915
T2	85468	1652
T3	105629	2769
T4	1606	0
T7	39374	0
T9	27812	50
T10	189613	10325
T11	0	19
T12	0	2017
T22	0	2403
T29	4436	104
T30	5572	132
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	646966534	49971347
T1	159591	915
T2	85468	1652
T3	105629	2769
T4	1606	0
T7	39374	0
T9	27812	50
T10	189613	10325
T11	0	19
T12	0	2017
T22	0	2403
T29	4436	104
T30	5572	132
T43	1805	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	11	78.57
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        unreachable      assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        0/1     ==>            storage[0] <= wdata_i;
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        0/1     ==>        assign rdata_int = storage_rdata;
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	646966534	0	0	0
DepthKnown_A	646966534	646807694	0	0
RvalidKnown_A	646966534	646807694	0	0
WreadyKnown_A	646966534	646807694	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	646966534	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646966534	0	0	0

DepthKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	646966534	0	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        unreachable      assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        unreachable            storage[0] <= wdata_i;
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Covered	Percent
Conditions	17	8	47.06
Logical	17	8	47.06
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	1	1	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==> (Unreachable)  
                                                             ==>

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==> (Unreachable)
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	646966534	0	0	0
DepthKnown_A	646966534	646807694	0	0
RvalidKnown_A	646966534	646807694	0	0
WreadyKnown_A	646966534	646807694	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	646966534	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646966534	0	0	0

DepthKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	646966534	0	0	0

Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T3 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T46,T58
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T29,T30
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (72'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	646610540	51984056	0	0
DepthKnown_A	646966534	646807694	0	0
RvalidKnown_A	646966534	646807694	0	0
WreadyKnown_A	646966534	646807694	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	646610540	51984056	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	646610540	51984056
T1	159591	24579
T2	85468	728
T3	105629	1224
T4	1606	0
T7	39374	0
T9	27812	738
T10	189613	6273
T11	0	120
T12	0	4537
T22	0	6210
T29	4436	849
T30	5572	817
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	646610540	51984056
T1	159591	24579
T2	85468	728
T3	105629	1224
T4	1606	0
T7	39374	0
T9	27812	738
T10	189613	6273
T11	0	120
T12	0	4537
T22	0	6210
T29	4436	849
T30	5572	817
T43	1805	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T3 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T3 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T29,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	646966534	26271894	0	0
DepthKnown_A	646966534	646807694	0	0
RvalidKnown_A	646966534	646807694	0	0
WreadyKnown_A	646966534	646807694	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	646966534	26271894	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	646966534	26271894
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	28581
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	646966534	26271894
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	28581
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T3 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T3 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	646966534	12919638	0	0
DepthKnown_A	646966534	646807694	0	0
RvalidKnown_A	646966534	646807694	0	0
WreadyKnown_A	646966534	646807694	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	646966534	12919638	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	646966534	12919638
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	6292
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	646966534	12919638
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	6292
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T3 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T29,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	646966534	26209019	0	0
DepthKnown_A	646966534	646807694	0	0
RvalidKnown_A	646966534	646807694	0	0
WreadyKnown_A	646966534	646807694	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	646966534	26209019	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	646966534	26209019
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	28581
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	646966534	646807694
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	646966534	26209019
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	28581
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	109817254	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	648366898	109817254
T1	159591	26266
T2	85468	10871
T3	105629	15551
T4	1606	281
T7	39374	300
T9	27812	783
T10	189613	19854
T29	4436	770
T30	5572	855
T43	1805	232

DepthKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	881	881
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T7	1	1
T9	1	1
T10	1	1
T29	1	1
T30	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	191582632	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	648366898	191582632
T1	159591	25694
T2	85468	10871
T3	105629	15551
T4	1606	281
T7	39374	1359
T9	27812	778
T10	189613	77014
T29	4436	770
T30	5572	855
T43	1805	232

DepthKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	881	881
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T7	1	1
T9	1	1
T10	1	1
T29	1	1
T30	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	12986729	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	648366898	12986729
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	6292
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	881	881
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T7	1	1
T9	1	1
T10	1	1
T29	1	1
T30	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	26286742	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	648366898	26286742
T1	159591	11178
T2	85468	2520
T3	105629	2192
T4	1606	208
T7	39374	0
T9	27812	432
T10	189613	28581
T11	0	68
T12	0	4278
T29	4436	96
T30	5572	96
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	881	881
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T7	1	1
T9	1	1
T10	1	1
T29	1	1
T30	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	27057403	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	648366898	27057403
T1	159591	915
T2	85468	1652
T3	105629	2769
T4	1606	0
T7	39374	0
T9	27812	50
T10	189613	2190
T11	0	37
T12	0	2017
T22	0	2403
T29	4436	104
T30	5572	132
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	881	881
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T7	1	1
T9	1	1
T10	1	1
T29	1	1
T30	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	50000603	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	648366898	50000603
T1	159591	915
T2	85468	1652
T3	105629	2769
T4	1606	0
T7	39374	0
T9	27812	50
T10	189613	10325
T11	0	19
T12	0	2017
T22	0	2403
T29	4436	104
T30	5572	132
T43	1805	0

DepthKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

RvalidKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

WreadyKnown_A

Name	Attempts	Real Successes
Total	648366898	648156678
T1	159591	159493
T2	85468	85407
T3	105629	105531
T4	1606	1511
T7	39374	39302
T9	27812	27741
T10	189613	189522
T29	4436	4368
T30	5572	5507
T43	1805	1708

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	881	881
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T7	1	1
T9	1	1
T10	1	1
T29	1	1
T30	1	1
T43	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.43	98.55	77.78			80.77	84.62	u_tlul_adapter_msgfifo

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.12	78.57	38.46			71.43	60.00