Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	59220987	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	59220987	0	0
T1	159591	13601	0	0
T2	85468	6699	0	0
T3	105629	10590	0	0
T4	1606	73	0	0
T7	39374	300	0	0
T9	27812	296	0	0
T10	189613	8379	0	0
T29	4436	570	0	0
T30	5572	627	0	0
T43	1805	232	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	648156678	0	0
T1	159591	159493	0	0
T2	85468	85407	0	0
T3	105629	105531	0	0
T4	1606	1511	0	0
T7	39374	39302	0	0
T9	27812	27741	0	0
T10	189613	189522	0	0
T29	4436	4368	0	0
T30	5572	5507	0	0
T43	1805	1708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	648156678	0	0
T1	159591	159493	0	0
T2	85468	85407	0	0
T3	105629	105531	0	0
T4	1606	1511	0	0
T7	39374	39302	0	0
T9	27812	27741	0	0
T10	189613	189522	0	0
T29	4436	4368	0	0
T30	5572	5507	0	0
T43	1805	1708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	648156678	0	0
T1	159591	159493	0	0
T2	85468	85407	0	0
T3	105629	105531	0	0
T4	1606	1511	0	0
T7	39374	39302	0	0
T9	27812	27741	0	0
T10	189613	189522	0	0
T29	4436	4368	0	0
T30	5572	5507	0	0
T43	1805	1708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T43	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	648366898	115295287	0	0
DepthKnown_A	648366898	648156678	0	0
RvalidKnown_A	648366898	648156678	0	0
WreadyKnown_A	648366898	648156678	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	115295287	0	0
T1	159591	13601	0	0
T2	85468	6699	0	0
T3	105629	10590	0	0
T4	1606	73	0	0
T7	39374	1359	0	0
T9	27812	296	0	0
T10	189613	38108	0	0
T29	4436	570	0	0
T30	5572	627	0	0
T43	1805	232	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	648156678	0	0
T1	159591	159493	0	0
T2	85468	85407	0	0
T3	105629	105531	0	0
T4	1606	1511	0	0
T7	39374	39302	0	0
T9	27812	27741	0	0
T10	189613	189522	0	0
T29	4436	4368	0	0
T30	5572	5507	0	0
T43	1805	1708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	648156678	0	0
T1	159591	159493	0	0
T2	85468	85407	0	0
T3	105629	105531	0	0
T4	1606	1511	0	0
T7	39374	39302	0	0
T9	27812	27741	0	0
T10	189613	189522	0	0
T29	4436	4368	0	0
T30	5572	5507	0	0
T43	1805	1708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	648156678	0	0
T1	159591	159493	0	0
T2	85468	85407	0	0
T3	105629	105531	0	0
T4	1606	1511	0	0
T7	39374	39302	0	0
T9	27812	27741	0	0
T10	189613	189522	0	0
T29	4436	4368	0	0
T30	5572	5507	0	0
T43	1805	1708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T43	1	1	0	0