Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	648366898	11950	0	0
entropy_period_rd_A	648366898	1640	0	0
intr_enable_rd_A	648366898	2570	0	0
prefix_0_rd_A	648366898	1891	0	0
prefix_10_rd_A	648366898	1718	0	0
prefix_1_rd_A	648366898	2004	0	0
prefix_2_rd_A	648366898	1910	0	0
prefix_3_rd_A	648366898	1787	0	0
prefix_4_rd_A	648366898	1792	0	0
prefix_5_rd_A	648366898	1783	0	0
prefix_6_rd_A	648366898	1870	0	0
prefix_7_rd_A	648366898	1860	0	0
prefix_8_rd_A	648366898	1596	0	0
prefix_9_rd_A	648366898	1971	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	11950	0	0
T14	197551	1613	0	0
T15	203901	2471	0	0
T34	487473	0	0	0
T36	0	1533	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	1216	0	0
T78	216207	0	0	0
T105	0	6	0	0
T111	0	558	0	0
T112	0	1308	0	0
T113	0	3	0	0
T114	0	290	0	0
T115	0	3	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1640	0	0
T14	197551	27	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	20	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	13	0	0
T78	216207	0	0	0
T90	0	29	0	0
T92	0	14	0	0
T105	0	121	0	0
T109	0	1	0	0
T111	0	3	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	27	0	0
T130	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	2570	0	0
T14	197551	25	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	19	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	25	0	0
T78	216207	0	0	0
T90	0	15	0	0
T92	0	2	0	0
T105	0	133	0	0
T109	0	6	0	0
T111	0	37	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	30	0	0
T130	0	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1891	0	0
T14	197551	30	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	47	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	12	0	0
T78	216207	0	0	0
T90	0	16	0	0
T92	0	6	0	0
T105	0	83	0	0
T109	0	2	0	0
T111	0	16	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	36	0	0
T130	0	12	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1718	0	0
T14	197551	21	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	16	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	20	0	0
T78	216207	0	0	0
T90	0	22	0	0
T92	0	28	0	0
T105	0	70	0	0
T111	0	2	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	53	0	0
T130	0	27	0	0
T131	0	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	2004	0	0
T14	197551	28	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	28	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	14	0	0
T78	216207	0	0	0
T90	0	28	0	0
T92	0	8	0	0
T105	0	75	0	0
T109	0	2	0	0
T111	0	27	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	59	0	0
T130	0	15	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1910	0	0
T14	197551	30	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	23	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	23	0	0
T78	216207	0	0	0
T90	0	29	0	0
T92	0	6	0	0
T105	0	66	0	0
T109	0	10	0	0
T111	0	14	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	28	0	0
T130	0	16	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1787	0	0
T14	197551	24	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	18	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	15	0	0
T78	216207	0	0	0
T90	0	30	0	0
T92	0	1	0	0
T105	0	90	0	0
T109	0	13	0	0
T111	0	7	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	43	0	0
T130	0	12	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1792	0	0
T14	197551	25	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	22	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	11	0	0
T78	216207	0	0	0
T90	0	24	0	0
T92	0	3	0	0
T105	0	85	0	0
T109	0	2	0	0
T111	0	22	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	33	0	0
T130	0	2	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1783	0	0
T14	197551	34	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	17	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	20	0	0
T78	216207	0	0	0
T90	0	20	0	0
T92	0	20	0	0
T105	0	67	0	0
T109	0	2	0	0
T111	0	10	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	6	0	0
T130	0	15	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1870	0	0
T14	197551	29	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	27	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	19	0	0
T78	216207	0	0	0
T90	0	15	0	0
T92	0	10	0	0
T105	0	85	0	0
T111	0	8	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	44	0	0
T130	0	4	0	0
T131	0	4	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1860	0	0
T14	197551	16	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	24	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	30	0	0
T78	216207	0	0	0
T90	0	16	0	0
T92	0	2	0	0
T105	0	63	0	0
T109	0	6	0	0
T111	0	15	0	0
T116	14362	0	0	0
T117	113964	0	0	0
T118	5340	0	0	0
T129	0	35	0	0
T130	0	24	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1596	0	0
T14	197551	19	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	19	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	35	0	0
T78	216207	0	0	0
T90	0	27	0	0
T92	0	7	0	0
T105	0	81	0	0
T111	0	20	0	0
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T117	113964	0	0	0
T118	5340	0	0	0
T129	0	20	0	0
T130	0	7	0	0
T131	0	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	648366898	1971	0	0
T14	197551	14	0	0
T15	203901	0	0	0
T34	487473	0	0	0
T36	0	12	0	0
T39	221480	0	0	0
T50	282521	0	0	0
T58	135428	0	0	0
T70	0	18	0	0
T78	216207	0	0	0
T90	0	21	0	0
T92	0	2	0	0
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T117	113964	0	0	0
T118	5340	0	0	0
T129	0	44	0	0
T130	0	31	0	0