Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173354 |
1 |
|
|
T4 |
1360 |
|
T10 |
75 |
|
T5 |
1911 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91271 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60198 |
1 |
|
|
T4 |
1343 |
|
T10 |
2 |
|
T5 |
1879 |
seven_bytes |
3136 |
1 |
|
|
T10 |
2 |
|
T13 |
17 |
|
T15 |
12 |
six_bytes |
3150 |
1 |
|
|
T10 |
2 |
|
T13 |
13 |
|
T15 |
8 |
five_bytes |
3063 |
1 |
|
|
T10 |
3 |
|
T13 |
14 |
|
T15 |
7 |
four_bytes |
3255 |
1 |
|
|
T10 |
4 |
|
T13 |
21 |
|
T15 |
18 |
three_bytes |
3040 |
1 |
|
|
T10 |
2 |
|
T13 |
21 |
|
T15 |
19 |
two_bytes |
3070 |
1 |
|
|
T10 |
1 |
|
T13 |
11 |
|
T15 |
10 |
one_byte |
3171 |
1 |
|
|
T10 |
2 |
|
T13 |
13 |
|
T15 |
13 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170011 |
1 |
|
|
T4 |
1326 |
|
T10 |
73 |
|
T5 |
1847 |
auto[1] |
3343 |
1 |
|
|
T4 |
34 |
|
T10 |
2 |
|
T5 |
64 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173354 |
1 |
|
|
T4 |
1360 |
|
T10 |
75 |
|
T5 |
1911 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173343 |
1 |
|
|
T4 |
1360 |
|
T10 |
75 |
|
T5 |
1911 |
auto[1] |
11 |
1 |
|
|
T6 |
1 |
|
T175 |
1 |
|
T176 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1148 |
1 |
|
|
T4 |
17 |
|
T5 |
32 |
|
T13 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3343 |
1 |
|
|
T4 |
34 |
|
T10 |
2 |
|
T5 |
64 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181148 |
1 |
|
|
T4 |
702 |
|
T5 |
2038 |
|
T13 |
266 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
95264 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63190 |
1 |
|
|
T4 |
689 |
|
T5 |
2010 |
|
T13 |
8 |
seven_bytes |
3264 |
1 |
|
|
T13 |
6 |
|
T15 |
25 |
|
T16 |
29 |
six_bytes |
3316 |
1 |
|
|
T13 |
9 |
|
T15 |
34 |
|
T16 |
33 |
five_bytes |
3295 |
1 |
|
|
T13 |
4 |
|
T15 |
14 |
|
T16 |
34 |
four_bytes |
3244 |
1 |
|
|
T13 |
6 |
|
T15 |
17 |
|
T16 |
24 |
three_bytes |
3174 |
1 |
|
|
T13 |
8 |
|
T15 |
20 |
|
T16 |
41 |
two_bytes |
3304 |
1 |
|
|
T13 |
8 |
|
T15 |
20 |
|
T16 |
31 |
one_byte |
3097 |
1 |
|
|
T13 |
13 |
|
T15 |
18 |
|
T16 |
21 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177752 |
1 |
|
|
T4 |
676 |
|
T5 |
1982 |
|
T13 |
260 |
auto[1] |
3396 |
1 |
|
|
T4 |
26 |
|
T5 |
56 |
|
T13 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181148 |
1 |
|
|
T4 |
702 |
|
T5 |
2038 |
|
T13 |
266 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181133 |
1 |
|
|
T4 |
701 |
|
T5 |
2038 |
|
T13 |
266 |
auto[1] |
15 |
1 |
|
|
T4 |
1 |
|
T6 |
2 |
|
T73 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1164 |
1 |
|
|
T4 |
13 |
|
T5 |
28 |
|
T13 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3396 |
1 |
|
|
T4 |
26 |
|
T5 |
56 |
|
T13 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
351096 |
1 |
|
|
T4 |
1426 |
|
T10 |
705 |
|
T5 |
2792 |
auto[1] |
510 |
1 |
|
|
T4 |
22 |
|
T5 |
44 |
|
T6 |
77 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
183579 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
124187 |
1 |
|
|
T4 |
1426 |
|
T10 |
18 |
|
T5 |
2792 |
seven_bytes |
6418 |
1 |
|
|
T10 |
21 |
|
T13 |
30 |
|
T15 |
34 |
six_bytes |
6110 |
1 |
|
|
T10 |
20 |
|
T13 |
21 |
|
T15 |
31 |
five_bytes |
6360 |
1 |
|
|
T10 |
18 |
|
T13 |
22 |
|
T15 |
47 |
four_bytes |
6218 |
1 |
|
|
T10 |
20 |
|
T13 |
38 |
|
T15 |
41 |
three_bytes |
6240 |
1 |
|
|
T10 |
25 |
|
T13 |
28 |
|
T15 |
59 |
two_bytes |
6331 |
1 |
|
|
T10 |
20 |
|
T13 |
32 |
|
T15 |
46 |
one_byte |
6163 |
1 |
|
|
T10 |
21 |
|
T13 |
33 |
|
T15 |
43 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344966 |
1 |
|
|
T4 |
1404 |
|
T10 |
699 |
|
T5 |
2748 |
auto[1] |
6640 |
1 |
|
|
T4 |
44 |
|
T10 |
6 |
|
T5 |
88 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
351606 |
1 |
|
|
T4 |
1448 |
|
T10 |
705 |
|
T5 |
2836 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
351587 |
1 |
|
|
T4 |
1448 |
|
T10 |
705 |
|
T5 |
2836 |
auto[1] |
19 |
1 |
|
|
T13 |
1 |
|
T35 |
2 |
|
T177 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2321 |
1 |
|
|
T4 |
22 |
|
T5 |
44 |
|
T13 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6640 |
1 |
|
|
T4 |
44 |
|
T10 |
6 |
|
T5 |
88 |