Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48629254	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

48026207

1

T1

16

T2

95

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53673129	1			T1	9		T2	45		T3	1
values[0x0]	20830216	1			T1	11		T2	51		T3	9
values[0x1]	22152116	1			T1	9		T2	55		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37377836	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59277625

1

T1

18

T2

106

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	305222	1			T11	7		T17	2		T7	4
valid_sources[0x01]	445447	1			T2	4		T11	8		T12	2
valid_sources[0x02]	374443	1			T9	1		T11	6		T12	2
valid_sources[0x03]	367468	1			T17	1		T7	5		T24	2
valid_sources[0x04]	307746	1			T12	1		T17	1		T7	7
valid_sources[0x05]	311654	1			T12	1		T17	1		T24	5
valid_sources[0x06]	322512	1			T11	1		T17	5		T24	19
valid_sources[0x07]	543269	1			T11	5		T12	1		T17	1
valid_sources[0x08]	312849	1			T2	1		T12	3		T17	3
valid_sources[0x09]	313845	1			T12	1		T7	18		T24	9
valid_sources[0x0a]	345156	1			T2	1		T12	4		T17	2
valid_sources[0x0b]	320205	1			T2	1		T11	6		T12	3
valid_sources[0x0c]	309230	1			T2	1		T12	4		T7	7
valid_sources[0x0d]	417293	1			T12	2		T17	2		T7	4
valid_sources[0x0e]	400678	1			T11	3		T12	2		T7	2
valid_sources[0x0f]	462746	1			T2	1		T9	8		T11	3
valid_sources[0x10]	305605	1			T2	1		T3	1		T12	2
valid_sources[0x11]	302580	1			T3	2		T9	12		T12	2
valid_sources[0x12]	310481	1			T11	1		T12	3		T17	1
valid_sources[0x13]	310659	1			T2	4		T11	1		T7	1
valid_sources[0x14]	309297	1			T2	1		T12	2		T17	6
valid_sources[0x15]	311700	1			T2	1		T11	7		T12	1
valid_sources[0x16]	308537	1			T11	6		T17	1		T7	4
valid_sources[0x17]	337050	1			T2	1		T12	2		T17	3
valid_sources[0x18]	308357	1			T7	4		T24	14		T48	6
valid_sources[0x19]	312871	1			T17	1		T7	3		T24	10
valid_sources[0x1a]	343871	1			T2	2		T11	4		T12	2
valid_sources[0x1b]	307879	1			T2	1		T12	3		T17	1
valid_sources[0x1c]	323674	1			T17	3		T7	4		T24	6
valid_sources[0x1d]	309165	1			T2	1		T11	8		T12	2
valid_sources[0x1e]	313975	1			T2	1		T11	4		T12	1
valid_sources[0x1f]	337435	1			T2	4		T12	2		T17	4
valid_sources[0x20]	325091	1			T2	1		T12	3		T17	4
valid_sources[0x21]	444732	1			T2	1		T11	2		T12	2
valid_sources[0x22]	326010	1			T2	2		T17	1		T7	5
valid_sources[0x23]	309793	1			T2	1		T3	1		T11	3
valid_sources[0x24]	308489	1			T11	2		T12	2		T17	6
valid_sources[0x25]	311214	1			T11	4		T12	5		T7	1
valid_sources[0x26]	358419	1			T9	7		T12	4		T17	2
valid_sources[0x27]	309180	1			T3	1		T12	1		T17	5
valid_sources[0x28]	308864	1			T12	2		T7	12		T24	12
valid_sources[0x29]	311930	1			T2	2		T11	5		T12	1
valid_sources[0x2a]	479477	1			T11	4		T12	2		T17	3
valid_sources[0x2b]	478165	1			T2	2		T17	3		T7	2
valid_sources[0x2c]	307571	1			T12	1		T17	4		T7	10
valid_sources[0x2d]	314690	1			T11	4		T12	3		T17	7
valid_sources[0x2e]	310765	1			T2	2		T12	6		T17	2
valid_sources[0x2f]	307670	1			T11	5		T12	1		T17	2
valid_sources[0x30]	343084	1			T11	2		T12	6		T17	7
valid_sources[0x31]	307971	1			T17	1		T7	1		T24	14
valid_sources[0x32]	309352	1			T2	1		T11	4		T12	2
valid_sources[0x33]	550981	1			T9	14		T11	4		T12	2
valid_sources[0x34]	322539	1			T2	1		T12	3		T17	3
valid_sources[0x35]	305348	1			T2	2		T11	4		T12	3
valid_sources[0x36]	307884	1			T12	4		T17	3		T7	3
valid_sources[0x37]	534115	1			T11	4		T12	1		T17	6
valid_sources[0x38]	502556	1			T9	5		T11	6		T12	1
valid_sources[0x39]	308723	1			T12	1		T17	2		T7	7
valid_sources[0x3a]	306860	1			T17	1		T7	7		T24	9
valid_sources[0x3b]	308524	1			T17	4		T7	6		T24	10
valid_sources[0x3c]	310097	1			T12	6		T17	3		T7	5
valid_sources[0x3d]	315333	1			T11	2		T12	5		T17	2
valid_sources[0x3e]	369263	1			T12	3		T7	1		T24	9
valid_sources[0x3f]	1310990	1			T2	1		T9	5		T17	3
valid_sources[0x40]	305966	1			T3	1		T12	4		T17	4
valid_sources[0x41]	309498	1			T17	1		T7	3		T24	12
valid_sources[0x42]	308917	1			T12	5		T17	2		T7	10
valid_sources[0x43]	309457	1			T11	2		T12	4		T7	4
valid_sources[0x44]	309772	1			T12	5		T17	1		T7	4
valid_sources[0x45]	377230	1			T2	2		T11	4		T17	6
valid_sources[0x46]	342404	1			T3	1		T17	9		T24	9
valid_sources[0x47]	444702	1			T2	1		T12	1		T17	1
valid_sources[0x48]	430674	1			T17	4		T7	8		T24	16
valid_sources[0x49]	308132	1			T2	4		T12	2		T17	1
valid_sources[0x4a]	491754	1			T9	4		T12	1		T7	4
valid_sources[0x4b]	308511	1			T2	1		T12	2		T17	1
valid_sources[0x4c]	310903	1			T12	1		T17	3		T7	5
valid_sources[0x4d]	314095	1			T12	6		T17	2		T7	9
valid_sources[0x4e]	316982	1			T12	5		T17	2		T7	7
valid_sources[0x4f]	305606	1			T12	2		T17	2		T24	13
valid_sources[0x50]	311917	1			T11	3		T12	3		T17	2
valid_sources[0x51]	308384	1			T3	1		T11	2		T12	1
valid_sources[0x52]	1128629	1			T11	3		T12	1		T24	13
valid_sources[0x53]	308310	1			T9	7		T12	3		T17	1
valid_sources[0x54]	312886	1			T2	1		T9	4		T12	1
valid_sources[0x55]	311714	1			T11	1		T12	1		T17	1
valid_sources[0x56]	306854	1			T2	1		T12	3		T24	8
valid_sources[0x57]	307818	1			T2	1		T17	2		T7	1
valid_sources[0x58]	306142	1			T11	1		T12	6		T17	2
valid_sources[0x59]	308788	1			T12	3		T17	1		T7	2
valid_sources[0x5a]	311788	1			T2	1		T9	1		T11	1
valid_sources[0x5b]	407875	1			T2	1		T11	4		T12	2
valid_sources[0x5c]	369609	1			T12	8		T17	3		T7	8
valid_sources[0x5d]	425488	1			T12	6		T17	5		T7	9
valid_sources[0x5e]	321769	1			T2	1		T11	12		T12	2
valid_sources[0x5f]	312378	1			T3	1		T12	2		T17	2
valid_sources[0x60]	307018	1			T2	2		T11	3		T12	1
valid_sources[0x61]	305417	1			T12	1		T17	1		T7	3
valid_sources[0x62]	310778	1			T11	2		T12	1		T7	6
valid_sources[0x63]	359395	1			T2	1		T11	7		T12	2
valid_sources[0x64]	314001	1			T2	2		T12	4		T7	6
valid_sources[0x65]	309464	1			T11	4		T12	6		T17	4
valid_sources[0x66]	314719	1			T11	1		T12	1		T17	3
valid_sources[0x67]	376838	1			T11	3		T12	1		T17	2
valid_sources[0x68]	308623	1			T11	8		T12	6		T17	1
valid_sources[0x69]	309017	1			T11	4		T17	1		T7	6
valid_sources[0x6a]	314176	1			T2	2		T11	2		T12	2
valid_sources[0x6b]	310378	1			T12	1		T17	2		T7	6
valid_sources[0x6c]	306166	1			T2	2		T9	1		T12	3
valid_sources[0x6d]	307146	1			T2	1		T12	5		T24	16
valid_sources[0x6e]	351399	1			T7	5		T24	9		T48	2
valid_sources[0x6f]	474152	1			T2	2		T12	3		T17	1
valid_sources[0x70]	308980	1			T2	1		T12	1		T17	4
valid_sources[0x71]	311795	1			T7	6		T24	7		T25	8
valid_sources[0x72]	307148	1			T11	4		T17	4		T7	13
valid_sources[0x73]	394518	1			T12	1		T17	2		T7	9
valid_sources[0x74]	561463	1			T12	3		T17	4		T7	4
valid_sources[0x75]	308683	1			T11	11		T12	1		T17	2
valid_sources[0x76]	307564	1			T12	1		T7	14		T24	17
valid_sources[0x77]	512287	1			T2	1		T3	1		T12	7
valid_sources[0x78]	311974	1			T7	2		T24	11		T48	8
valid_sources[0x79]	305526	1			T12	2		T17	4		T7	1
valid_sources[0x7a]	309324	1			T11	1		T12	2		T7	12
valid_sources[0x7b]	890195	1			T12	1		T17	4		T7	1
valid_sources[0x7c]	370419	1			T11	2		T12	3		T17	9
valid_sources[0x7d]	318022	1			T7	3		T24	12		T48	6
valid_sources[0x7e]	316103	1			T2	2		T17	1		T7	2
valid_sources[0x7f]	309271	1			T9	35		T12	1		T17	4
valid_sources[0x80]	309068	1			T11	3		T12	1		T17	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21223772

1

T1

6

T2

22

T9

77

values[0x0]

all_enables

biggest_size

14078822

1

T1

6

T2

38

T3

3

values[0x1]

all_enables

biggest_size

12723613

1

T1

4

T2

35

T9

37