Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48718641

1

T1

13

T2

56

T3

14

full_word

48031808

1

T1

16

T2

95

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	96750159	1			T1	29		T2	151		T3	17
auto[TlIntgErrCmd]	95	1			T134	3		T135	3		T136	2
auto[TlIntgErrData]	104	1			T134	6		T135	6		T136	2
auto[TlIntgErrBoth]	91	1			T134	1		T135	1		T136	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53694944

1

T1

9

T2

45

T3

1

auto[1]

43055505

1

T1

20

T2

106

T3

16

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	32469394	1			T1	3		T2	23		T3	1
auto[TlIntgErrNone]	partial	auto[1]	16248974	1			T1	10		T2	33		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	21225413	1			T1	6		T2	22		T9	77
auto[TlIntgErrNone]	full_word	auto[1]	26806378	1			T1	10		T2	73		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T134	2		T135	1		T136	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T134	1		T135	1		T160	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T160	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T135	1		T178	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T134	3		T135	5		T136	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T134	3		T135	1		T160	3
auto[TlIntgErrData]	full_word	auto[1]	4	1			T180	1		T181	1		T182	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T134	1		T136	2		T160	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T135	1		T136	4		T160	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T180	1		T183	1		T184	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T178	1		T179	1		-	-