Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	663284326	57770	0	0
RunThenComplete_M	663284326	729332	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663284326	57770	0	0
T7	111779	17	0	0
T8	30341	4	0	0
T11	8427	3	0	0
T12	8740	3	0	0
T17	2823	3	0	0
T24	8456	3	0	0
T25	6776	2	0	0
T33	0	129	0	0
T47	0	73	0	0
T48	7922	3	0	0
T49	4080	0	0	0
T50	2273	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	663284326	729332	0	0
T7	111779	51	0	0
T8	30341	12	0	0
T11	8427	10	0	0
T12	8740	10	0	0
T17	2823	10	0	0
T24	8456	17	0	0
T25	6776	11	0	0
T33	0	303	0	0
T47	0	74	0	0
T48	7922	11	0	0
T49	4080	0	0	0
T50	2273	0	0	0