Unified Coverage Report :: Module Instance :: tb.dut.u_tlul_adapter_msgfifo.u

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T9 T11 T12 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T9 T11 T12 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T9 T11 T12 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T11,T12,T48
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T11,T12
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T12



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	663284326	53778023	0	0
DepthKnown_A	663284326	663112333	0	0
RvalidKnown_A	663284326	663112333	0	0
WreadyKnown_A	663284326	663112333	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	663284326	53778023	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	663284326	53778023
T7	111779	0
T9	1230	28
T11	8427	250
T12	8740	282
T17	2823	72
T19	0	5
T24	8456	750
T25	6776	250
T33	0	769
T47	0	3549
T48	7922	104
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	663284326	53778023
T7	111779	0
T9	1230	28
T11	8427	250
T12	8740	282
T17	2823	72
T19	0	5
T24	8456	750
T25	6776	250
T33	0	769
T47	0	3549
T48	7922	104
T49	4080	0
T50	2273	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	11	78.57
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        unreachable      assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        0/1     ==>            storage[0] <= wdata_i;
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        0/1     ==>        assign rdata_int = storage_rdata;
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	663284326	0	0	0
DepthKnown_A	663284326	663112333	0	0
RvalidKnown_A	663284326	663112333	0	0
WreadyKnown_A	663284326	663112333	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	663284326	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663284326	0	0	0

DepthKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	663284326	0	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        unreachable      assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        unreachable            storage[0] <= wdata_i;
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Covered	Percent
Conditions	17	8	47.06
Logical	17	8	47.06
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	1	1	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==> (Unreachable)  
                                                             ==>

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==> (Unreachable)
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	663284326	0	0	0
DepthKnown_A	663284326	663112333	0	0
RvalidKnown_A	663284326	663112333	0	0
WreadyKnown_A	663284326	663112333	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	663284326	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663284326	0	0	0

DepthKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	663284326	0	0	0

Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T9 T11 T12 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T13
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T11,T12
1	0	1	Covered	T11,T12,T17
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T12

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T12

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T17
1	0	Covered	T9,T11,T12
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (72'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T11,T12
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T12



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	662945138	53484262	0	0
DepthKnown_A	663284326	663112333	0	0
RvalidKnown_A	663284326	663112333	0	0
WreadyKnown_A	663284326	663112333	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	662945138	53484262	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	662945138	53484262
T7	111779	0
T9	1230	5
T11	8427	396
T12	8740	369
T17	2823	710
T19	0	2753
T24	8456	1547
T25	6776	918
T33	0	18278
T47	0	360
T48	7922	618
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	662945138	53484262
T7	111779	0
T9	1230	5
T11	8427	396
T12	8740	369
T17	2823	710
T19	0	2753
T24	8456	1547
T25	6776	918
T33	0	18278
T47	0	360
T48	7922	618
T49	4080	0
T50	2273	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T9 T11 T12 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T9 T11 T12 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T9 T11 T12 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T11,T12,T48
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T11,T12
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T12



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	663284326	27945264	0	0
DepthKnown_A	663284326	663112333	0	0
RvalidKnown_A	663284326	663112333	0	0
WreadyKnown_A	663284326	663112333	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	663284326	27945264	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	663284326	27945264
T7	111779	0
T9	1230	68
T11	8427	201
T12	8740	128
T17	2823	48
T19	0	84
T24	8456	182
T25	6776	388
T33	0	9302
T47	0	10483
T48	7922	96
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	663284326	27945264
T7	111779	0
T9	1230	68
T11	8427	201
T12	8740	128
T17	2823	48
T19	0	84
T24	8456	182
T25	6776	388
T33	0	9302
T47	0	10483
T48	7922	96
T49	4080	0
T50	2273	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T9 T11 T12 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T9 T11 T12 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T9 T11 T12 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T11,T12
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T12



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	663284326	13095608	0	0
DepthKnown_A	663284326	663112333	0	0
RvalidKnown_A	663284326	663112333	0	0
WreadyKnown_A	663284326	663112333	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	663284326	13095608	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	663284326	13095608
T4	0	3236
T7	111779	0
T9	1230	68
T11	8427	48
T12	8740	48
T17	2823	48
T19	0	84
T24	8456	0
T25	6776	388
T33	0	9302
T47	0	2336
T48	7922	96
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	663284326	13095608
T4	0	3236
T7	111779	0
T9	1230	68
T11	8427	48
T12	8740	48
T17	2823	48
T19	0	84
T24	8456	0
T25	6776	388
T33	0	9302
T47	0	2336
T48	7922	96
T49	4080	0
T50	2273	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T9 T11 T12 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T9 T11 T12 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T11,T12,T48
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T12

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T12

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T47
1	0	Covered	T9,T11,T12
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T11,T12
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T11,T12



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	663284326	27898024	0	0
DepthKnown_A	663284326	663112333	0	0
RvalidKnown_A	663284326	663112333	0	0
WreadyKnown_A	663284326	663112333	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	663284326	27898024	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	663284326	27898024
T4	0	14408
T7	111779	0
T9	1230	68
T11	8427	201
T12	8740	128
T17	2823	48
T19	0	84
T24	8456	0
T25	6776	388
T33	0	9302
T47	0	10483
T48	7922	96
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	663284326	663112333
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	663284326	27898024
T4	0	14408
T7	111779	0
T9	1230	68
T11	8427	201
T12	8740	128
T17	2823	48
T19	0	84
T24	8456	0
T25	6776	388
T33	0	9302
T47	0	10483
T48	7922	96
T49	4080	0
T50	2273	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	664550221	112926943	0	0
DepthKnown_A	664550221	664330493	0	0
RvalidKnown_A	664550221	664330493	0	0
WreadyKnown_A	664550221	664330493	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	664550221	112926943
T1	1569	29
T2	2840	151
T3	1235	17
T7	111779	1268
T9	1230	242
T11	8427	476
T12	8740	531
T17	2823	572
T24	8456	5934
T48	7922	704

DepthKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	884	884
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T9	1	1
T11	1	1
T12	1	1
T17	1	1
T24	1	1
T48	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	664550221	206807471	0	0
DepthKnown_A	664550221	664330493	0	0
RvalidKnown_A	664550221	664330493	0	0
WreadyKnown_A	664550221	664330493	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	664550221	206807471
T1	1569	139
T2	2840	151
T3	1235	71
T7	111779	5753
T9	1230	231
T11	8427	2040
T12	8740	1727
T17	2823	572
T24	8456	3334
T48	7922	704

DepthKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	884	884
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T9	1	1
T11	1	1
T12	1	1
T17	1	1
T24	1	1
T48	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	664550221	13180177	0	0
DepthKnown_A	664550221	664330493	0	0
RvalidKnown_A	664550221	664330493	0	0
WreadyKnown_A	664550221	664330493	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	664550221	13180177
T7	111779	0
T9	1230	68
T11	8427	48
T12	8740	48
T17	2823	48
T19	0	84
T24	8456	386
T25	6776	388
T33	0	9302
T47	0	2336
T48	7922	96
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	884	884
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T9	1	1
T11	1	1
T12	1	1
T17	1	1
T24	1	1
T48	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	664550221	27963131	0	0
DepthKnown_A	664550221	664330493	0	0
RvalidKnown_A	664550221	664330493	0	0
WreadyKnown_A	664550221	664330493	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	664550221	27963131
T7	111779	0
T9	1230	68
T11	8427	201
T12	8740	128
T17	2823	48
T19	0	84
T24	8456	182
T25	6776	388
T33	0	9302
T47	0	10483
T48	7922	96
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	884	884
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T9	1	1
T11	1	1
T12	1	1
T17	1	1
T24	1	1
T48	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	664550221	28094563	0	0
DepthKnown_A	664550221	664330493	0	0
RvalidKnown_A	664550221	664330493	0	0
WreadyKnown_A	664550221	664330493	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	664550221	28094563
T7	111779	0
T9	1230	39
T11	8427	55
T12	8740	73
T17	2823	72
T19	0	5
T24	8456	813
T25	6776	250
T33	0	769
T47	0	797
T48	7922	104
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	884	884
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T9	1	1
T11	1	1
T12	1	1
T17	1	1
T24	1	1
T48	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	664550221	53809607	0	0
DepthKnown_A	664550221	664330493	0	0
RvalidKnown_A	664550221	664330493	0	0
WreadyKnown_A	664550221	664330493	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	664550221	53809607
T7	111779	0
T9	1230	28
T11	8427	250
T12	8740	282
T17	2823	72
T19	0	5
T24	8456	750
T25	6776	250
T33	0	769
T47	0	3549
T48	7922	104
T49	4080	0
T50	2273	0

DepthKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

RvalidKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

WreadyKnown_A

Name	Attempts	Real Successes
Total	664550221	664330493
T1	1569	1486
T2	2840	2776
T3	1235	1143
T7	111779	111696
T9	1230	1049
T11	8427	8342
T12	8740	8689
T17	2823	2769
T24	8456	8342
T48	7922	7871

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	884	884
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T9	1	1
T11	1	1
T12	1	1
T17	1	1
T24	1	1
T48	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.43	98.55	77.78			80.77	84.62	u_tlul_adapter_msgfifo

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.12	78.57	38.46			71.43	60.00