Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182608 |
1 |
|
|
T9 |
738 |
|
T4 |
154 |
|
T11 |
3 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
102015 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
56508 |
1 |
|
|
T9 |
22 |
|
T4 |
152 |
|
T11 |
3 |
seven_bytes |
3434 |
1 |
|
|
T9 |
15 |
|
T32 |
7 |
|
T15 |
46 |
six_bytes |
3504 |
1 |
|
|
T9 |
31 |
|
T32 |
6 |
|
T15 |
33 |
five_bytes |
3361 |
1 |
|
|
T9 |
27 |
|
T32 |
7 |
|
T15 |
35 |
four_bytes |
3390 |
1 |
|
|
T9 |
14 |
|
T32 |
5 |
|
T15 |
43 |
three_bytes |
3432 |
1 |
|
|
T9 |
17 |
|
T32 |
5 |
|
T15 |
46 |
two_bytes |
3501 |
1 |
|
|
T9 |
25 |
|
T32 |
8 |
|
T15 |
41 |
one_byte |
3463 |
1 |
|
|
T9 |
15 |
|
T32 |
9 |
|
T15 |
40 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179328 |
1 |
|
|
T9 |
726 |
|
T4 |
150 |
|
T11 |
3 |
auto[1] |
3280 |
1 |
|
|
T9 |
12 |
|
T4 |
4 |
|
T12 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182608 |
1 |
|
|
T9 |
738 |
|
T4 |
154 |
|
T11 |
3 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182592 |
1 |
|
|
T9 |
738 |
|
T4 |
154 |
|
T11 |
3 |
auto[1] |
16 |
1 |
|
|
T5 |
3 |
|
T139 |
1 |
|
T111 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1074 |
1 |
|
|
T9 |
2 |
|
T4 |
2 |
|
T12 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3280 |
1 |
|
|
T9 |
12 |
|
T4 |
4 |
|
T12 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174626 |
1 |
|
|
T9 |
1571 |
|
T4 |
129 |
|
T12 |
81 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
96105 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55809 |
1 |
|
|
T9 |
46 |
|
T4 |
126 |
|
T12 |
80 |
seven_bytes |
3199 |
1 |
|
|
T9 |
45 |
|
T32 |
1 |
|
T15 |
39 |
six_bytes |
3333 |
1 |
|
|
T9 |
43 |
|
T32 |
1 |
|
T15 |
37 |
five_bytes |
3219 |
1 |
|
|
T9 |
27 |
|
T32 |
3 |
|
T15 |
52 |
four_bytes |
3249 |
1 |
|
|
T9 |
43 |
|
T32 |
2 |
|
T15 |
40 |
three_bytes |
3273 |
1 |
|
|
T9 |
47 |
|
T32 |
1 |
|
T15 |
41 |
two_bytes |
3158 |
1 |
|
|
T9 |
34 |
|
T15 |
48 |
|
T110 |
28 |
one_byte |
3281 |
1 |
|
|
T9 |
38 |
|
T32 |
1 |
|
T15 |
41 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171406 |
1 |
|
|
T9 |
1553 |
|
T4 |
123 |
|
T12 |
79 |
auto[1] |
3220 |
1 |
|
|
T9 |
18 |
|
T4 |
6 |
|
T12 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174626 |
1 |
|
|
T9 |
1571 |
|
T4 |
129 |
|
T12 |
81 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174615 |
1 |
|
|
T9 |
1571 |
|
T4 |
129 |
|
T12 |
81 |
auto[1] |
11 |
1 |
|
|
T178 |
1 |
|
T86 |
1 |
|
T179 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1071 |
1 |
|
|
T9 |
3 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3220 |
1 |
|
|
T9 |
18 |
|
T4 |
6 |
|
T12 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
358765 |
1 |
|
|
T9 |
3269 |
|
T4 |
513 |
|
T12 |
264 |
auto[1] |
398 |
1 |
|
|
T4 |
6 |
|
T5 |
35 |
|
T6 |
30 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
201878 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
108745 |
1 |
|
|
T9 |
92 |
|
T4 |
513 |
|
T12 |
260 |
seven_bytes |
7045 |
1 |
|
|
T9 |
85 |
|
T14 |
7 |
|
T32 |
3 |
six_bytes |
6876 |
1 |
|
|
T9 |
88 |
|
T14 |
12 |
|
T32 |
7 |
five_bytes |
7034 |
1 |
|
|
T9 |
106 |
|
T14 |
11 |
|
T32 |
5 |
four_bytes |
6935 |
1 |
|
|
T9 |
88 |
|
T14 |
11 |
|
T32 |
7 |
three_bytes |
6870 |
1 |
|
|
T9 |
75 |
|
T14 |
5 |
|
T32 |
7 |
two_bytes |
6904 |
1 |
|
|
T9 |
84 |
|
T14 |
16 |
|
T32 |
7 |
one_byte |
6876 |
1 |
|
|
T9 |
82 |
|
T14 |
10 |
|
T32 |
3 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
352668 |
1 |
|
|
T9 |
3233 |
|
T4 |
507 |
|
T12 |
256 |
auto[1] |
6495 |
1 |
|
|
T9 |
36 |
|
T4 |
12 |
|
T12 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359163 |
1 |
|
|
T9 |
3269 |
|
T4 |
519 |
|
T12 |
264 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359144 |
1 |
|
|
T9 |
3269 |
|
T4 |
519 |
|
T12 |
264 |
auto[1] |
19 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T50 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2134 |
1 |
|
|
T9 |
8 |
|
T4 |
6 |
|
T12 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6495 |
1 |
|
|
T9 |
36 |
|
T4 |
12 |
|
T12 |
8 |