Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48180331	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

48474148

1

T1

67

T2

7

T3

178

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53122244	1			T1	37		T2	1		T3	66
values[0x0]	21109324	1			T1	37		T2	11		T3	64
values[0x1]	22422911	1			T1	50		T2	16		T3	72

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37038259	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59616220

1

T1

79

T2

10

T3

184

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	307887	1			T1	1		T10	26		T9	11
valid_sources[0x01]	307809	1			T9	18		T16	12		T4	4
valid_sources[0x02]	305735	1			T9	12		T44	1		T45	3
valid_sources[0x03]	305832	1			T1	1		T9	18		T16	3
valid_sources[0x04]	534992	1			T1	1		T9	16		T16	5
valid_sources[0x05]	305088	1			T1	1		T9	15		T16	3
valid_sources[0x06]	304557	1			T1	3		T9	11		T16	1
valid_sources[0x07]	307491	1			T9	19		T16	1		T44	1
valid_sources[0x08]	1416921	1			T9	10		T16	6		T44	1
valid_sources[0x09]	305878	1			T1	2		T9	14		T46	3
valid_sources[0x0a]	321600	1			T9	17		T16	2		T44	1
valid_sources[0x0b]	309515	1			T9	12		T16	4		T4	5
valid_sources[0x0c]	320041	1			T9	15		T16	5		T45	1
valid_sources[0x0d]	461855	1			T10	46		T9	15		T44	1
valid_sources[0x0e]	372452	1			T9	16		T16	18		T4	11
valid_sources[0x0f]	304682	1			T9	14		T16	1		T4	5
valid_sources[0x10]	317039	1			T9	19		T16	1		T4	3
valid_sources[0x11]	310827	1			T2	7		T9	18		T16	2
valid_sources[0x12]	306664	1			T9	15		T16	7		T44	2
valid_sources[0x13]	305824	1			T9	17		T16	10		T4	3
valid_sources[0x14]	375197	1			T42	1		T9	12		T16	2
valid_sources[0x15]	303343	1			T3	4		T10	6		T9	15
valid_sources[0x16]	308226	1			T1	1		T9	15		T16	3
valid_sources[0x17]	683565	1			T1	1		T9	15		T4	2
valid_sources[0x18]	340271	1			T3	3		T9	18		T44	2
valid_sources[0x19]	305026	1			T9	9		T45	22		T4	10
valid_sources[0x1a]	308143	1			T3	24		T10	19		T9	16
valid_sources[0x1b]	307134	1			T9	16		T44	1		T4	7
valid_sources[0x1c]	309078	1			T9	22		T45	21		T46	3
valid_sources[0x1d]	469692	1			T9	20		T16	4		T4	10
valid_sources[0x1e]	306712	1			T9	18		T44	1		T45	20
valid_sources[0x1f]	428068	1			T9	17		T16	12		T46	2
valid_sources[0x20]	310833	1			T1	1		T9	14		T16	2
valid_sources[0x21]	307342	1			T1	4		T9	6		T4	1
valid_sources[0x22]	305879	1			T1	2		T3	4		T9	9
valid_sources[0x23]	305788	1			T9	13		T16	1		T4	4
valid_sources[0x24]	312042	1			T1	2		T42	1		T9	12
valid_sources[0x25]	308847	1			T1	2		T9	12		T16	17
valid_sources[0x26]	522812	1			T1	2		T10	22		T9	18
valid_sources[0x27]	305324	1			T9	16		T4	14		T46	3
valid_sources[0x28]	308627	1			T9	16		T16	3		T4	1
valid_sources[0x29]	334806	1			T10	25		T9	15		T44	1
valid_sources[0x2a]	308718	1			T9	19		T16	7		T4	3
valid_sources[0x2b]	308596	1			T9	14		T16	4		T44	1
valid_sources[0x2c]	526147	1			T9	16		T46	4		T29	20
valid_sources[0x2d]	304678	1			T9	21		T44	1		T45	11
valid_sources[0x2e]	828613	1			T2	3		T42	1		T9	17
valid_sources[0x2f]	306011	1			T9	17		T16	1		T45	1
valid_sources[0x30]	714506	1			T9	15		T16	7		T4	4
valid_sources[0x31]	498326	1			T42	1		T10	13		T9	11
valid_sources[0x32]	307104	1			T1	2		T42	3		T9	18
valid_sources[0x33]	419435	1			T10	1		T9	22		T16	3
valid_sources[0x34]	306636	1			T9	13		T16	15		T45	5
valid_sources[0x35]	305290	1			T1	1		T9	15		T16	1
valid_sources[0x36]	307271	1			T1	2		T9	17		T16	3
valid_sources[0x37]	306446	1			T2	2		T10	25		T9	22
valid_sources[0x38]	306961	1			T1	2		T42	1		T9	11
valid_sources[0x39]	304214	1			T3	5		T9	16		T16	6
valid_sources[0x3a]	303609	1			T3	1		T9	18		T44	1
valid_sources[0x3b]	307219	1			T9	18		T44	1		T4	4
valid_sources[0x3c]	307585	1			T9	9		T44	2		T4	6
valid_sources[0x3d]	305616	1			T3	12		T42	1		T10	1
valid_sources[0x3e]	308589	1			T9	15		T44	1		T4	3
valid_sources[0x3f]	309432	1			T9	18		T16	2		T44	1
valid_sources[0x40]	304453	1			T9	15		T16	7		T44	2
valid_sources[0x41]	368781	1			T1	1		T9	18		T16	3
valid_sources[0x42]	306841	1			T2	1		T9	17		T16	2
valid_sources[0x43]	306250	1			T9	17		T4	2		T46	3
valid_sources[0x44]	306307	1			T3	2		T10	5		T9	22
valid_sources[0x45]	356261	1			T9	12		T16	10		T4	1
valid_sources[0x46]	304237	1			T9	16		T16	10		T46	5
valid_sources[0x47]	305034	1			T9	21		T16	1		T45	8
valid_sources[0x48]	309353	1			T9	12		T16	2		T8	2
valid_sources[0x49]	312458	1			T1	1		T10	15		T9	12
valid_sources[0x4a]	328023	1			T9	12		T16	6		T44	2
valid_sources[0x4b]	308910	1			T9	14		T16	2		T45	1
valid_sources[0x4c]	307478	1			T42	1		T9	16		T16	8
valid_sources[0x4d]	307592	1			T9	16		T16	1		T44	1
valid_sources[0x4e]	305936	1			T3	31		T10	30		T9	12
valid_sources[0x4f]	306547	1			T9	14		T16	4		T45	13
valid_sources[0x50]	307817	1			T42	1		T9	12		T45	4
valid_sources[0x51]	309494	1			T9	10		T16	1		T4	1
valid_sources[0x52]	315571	1			T9	15		T16	6		T8	5
valid_sources[0x53]	307900	1			T9	24		T16	4		T44	1
valid_sources[0x54]	1003767	1			T9	14		T16	13		T44	3
valid_sources[0x55]	327293	1			T9	10		T16	4		T45	7
valid_sources[0x56]	312571	1			T9	16		T4	3		T46	5
valid_sources[0x57]	307198	1			T9	16		T16	2		T44	3
valid_sources[0x58]	307604	1			T10	46		T9	16		T16	4
valid_sources[0x59]	307182	1			T9	10		T16	1		T44	1
valid_sources[0x5a]	339618	1			T10	7		T9	13		T44	3
valid_sources[0x5b]	315788	1			T1	2		T9	17		T16	4
valid_sources[0x5c]	368045	1			T1	1		T3	15		T9	16
valid_sources[0x5d]	673763	1			T10	4		T9	11		T16	1
valid_sources[0x5e]	308749	1			T9	16		T4	1		T46	3
valid_sources[0x5f]	308443	1			T1	1		T9	19		T16	3
valid_sources[0x60]	307543	1			T1	3		T9	24		T16	6
valid_sources[0x61]	307233	1			T1	2		T3	8		T9	15
valid_sources[0x62]	310637	1			T1	1		T9	18		T46	4
valid_sources[0x63]	306716	1			T9	16		T16	4		T44	1
valid_sources[0x64]	304689	1			T3	13		T42	1		T9	16
valid_sources[0x65]	308933	1			T1	2		T9	12		T16	3
valid_sources[0x66]	305827	1			T1	1		T2	3		T10	22
valid_sources[0x67]	380506	1			T10	49		T9	19		T16	2
valid_sources[0x68]	457808	1			T10	46		T9	17		T16	5
valid_sources[0x69]	306971	1			T9	19		T16	2		T45	12
valid_sources[0x6a]	398284	1			T9	16		T16	2		T45	1
valid_sources[0x6b]	307441	1			T1	1		T3	6		T9	15
valid_sources[0x6c]	308716	1			T9	20		T16	3		T44	1
valid_sources[0x6d]	307150	1			T10	4		T9	18		T44	2
valid_sources[0x6e]	310224	1			T9	18		T16	7		T44	1
valid_sources[0x6f]	307234	1			T1	1		T42	2		T9	14
valid_sources[0x70]	308623	1			T9	11		T4	2		T46	2
valid_sources[0x71]	305621	1			T1	4		T9	9		T45	10
valid_sources[0x72]	308964	1			T1	2		T9	15		T16	2
valid_sources[0x73]	305824	1			T9	12		T16	8		T4	3
valid_sources[0x74]	415269	1			T1	1		T9	12		T44	1
valid_sources[0x75]	309121	1			T1	1		T9	10		T16	5
valid_sources[0x76]	304469	1			T9	20		T16	2		T4	2
valid_sources[0x77]	310176	1			T1	3		T2	2		T9	21
valid_sources[0x78]	451207	1			T9	14		T16	1		T45	11
valid_sources[0x79]	308586	1			T9	18		T16	4		T45	3
valid_sources[0x7a]	308195	1			T42	1		T9	17		T16	3
valid_sources[0x7b]	308590	1			T9	11		T16	3		T45	2
valid_sources[0x7c]	304985	1			T9	13		T4	2		T8	8
valid_sources[0x7d]	327182	1			T1	4		T9	16		T16	1
valid_sources[0x7e]	930554	1			T9	17		T16	4		T4	1
valid_sources[0x7f]	308054	1			T9	14		T44	1		T45	6
valid_sources[0x80]	379828	1			T9	15		T16	5		T45	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21138895

1

T1

13

T2

1

T3

58

values[0x0]

all_enables

biggest_size

14344897

1

T1

25

T2

3

T3

57

values[0x1]

all_enables

biggest_size

12990356

1

T1

29

T2

3

T3

63