Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48224709

1

T1

57

T2

21

T3

24

full_word

48476866

1

T1

67

T2

7

T3

178

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	96701275	1			T1	124		T2	28		T3	202
auto[TlIntgErrCmd]	103	1			T127	6		T128	7		T129	3
auto[TlIntgErrData]	93	1			T127	5		T128	9		T129	2
auto[TlIntgErrBoth]	104	1			T127	9		T128	4		T129	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53132108

1

T1

37

T2

1

T3

66

auto[1]

43569467

1

T1

87

T2

27

T3

136

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	31992330	1			T1	24		T3	8		T42	1
auto[TlIntgErrNone]	partial	auto[1]	16232114	1			T1	33		T2	21		T3	16
auto[TlIntgErrNone]	full_word	auto[0]	21139633	1			T1	13		T2	1		T3	58
auto[TlIntgErrNone]	full_word	auto[1]	27337198	1			T1	54		T2	6		T3	120
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T127	2		T128	4		T129	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T127	4		T128	3		T129	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T183	1		T182	1		T184	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T185	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T127	3		T128	2		T181	4
auto[TlIntgErrData]	partial	auto[1]	38	1			T127	2		T128	4		T129	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T129	1		T181	1		T182	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T128	3		T183	1		T186	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T127	2		T128	1		T129	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T127	5		T128	2		T129	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T127	1		T181	1		T183	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T127	1		T128	1		T183	2