Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	607426096	56684	0	0
RunThenComplete_M	607426096	745361	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607426096	56684	0	0
T4	44086	5	0	0
T7	62595	8	0	0
T8	119742	16	0	0
T9	532444	81	0	0
T10	5178	3	0	0
T16	11972	3	0	0
T29	0	34	0	0
T43	1745	0	0	0
T44	1420	0	0	0
T45	8079	3	0	0
T46	11347	3	0	0
T48	0	3	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	607426096	745361	0	0
T3	5807	1	0	0
T4	44086	24	0	0
T7	0	24	0	0
T8	0	48	0	0
T9	532444	431	0	0
T10	5178	11	0	0
T16	11972	11	0	0
T29	0	88	0	0
T42	1758	0	0	0
T43	1745	0	0	0
T44	1420	0	0	0
T45	8079	11	0	0
T46	11347	11	0	0