Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608684823	58854008	0	0
DataKnown_AKnownEnable	608684823	608477408	0	0
DepthKnown_A	608684823	608477408	0	0
RvalidKnown_A	608684823	608477408	0	0
WreadyKnown_A	608684823	608477408	0	0
gen_passthru_fifo.paramCheckPass	882	882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	58854008	0	0
T1	1564	124	0	0
T2	2038	28	0	0
T3	5807	136	0	0
T9	532444	28200	0	0
T10	5178	624	0	0
T16	11972	518	0	0
T42	1758	32	0	0
T43	1745	21	0	0
T44	1420	139	0	0
T45	8079	519	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	882	882	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608684823	110080453	0	0
DataKnown_AKnownEnable	608684823	608477408	0	0
DepthKnown_A	608684823	608477408	0	0
RvalidKnown_A	608684823	608477408	0	0
WreadyKnown_A	608684823	608477408	0	0
gen_passthru_fifo.paramCheckPass	882	882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	110080453	0	0
T1	1564	124	0	0
T2	2038	28	0	0
T3	5807	592	0	0
T9	532444	28200	0	0
T10	5178	624	0	0
T16	11972	2362	0	0
T42	1758	32	0	0
T43	1745	50	0	0
T44	1420	139	0	0
T45	8079	519	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	608477408	0	0
T1	1564	1510	0	0
T2	2038	1964	0	0
T3	5807	5677	0	0
T9	532444	532361	0	0
T10	5178	5119	0	0
T16	11972	11882	0	0
T42	1758	1663	0	0
T43	1745	1691	0	0
T44	1420	1344	0	0
T45	8079	8015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	882	882	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0