Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	608684823	7736	0	0
entropy_period_rd_A	608684823	1686	0	0
intr_enable_rd_A	608684823	2107	0	0
prefix_0_rd_A	608684823	1287	0	0
prefix_10_rd_A	608684823	1414	0	0
prefix_1_rd_A	608684823	1336	0	0
prefix_2_rd_A	608684823	1315	0	0
prefix_3_rd_A	608684823	1313	0	0
prefix_4_rd_A	608684823	1311	0	0
prefix_5_rd_A	608684823	1386	0	0
prefix_6_rd_A	608684823	1456	0	0
prefix_7_rd_A	608684823	1347	0	0
prefix_8_rd_A	608684823	1415	0	0
prefix_9_rd_A	608684823	1275	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	7736	0	0
T15	495458	0	0	0
T32	279318	2713	0	0
T33	0	1091	0	0
T39	676499	0	0	0
T70	0	1506	0	0
T95	310133	0	0	0
T127	0	4	0	0
T133	0	2	0	0
T134	0	97	0	0
T135	0	102	0	0
T136	0	2	0	0
T137	0	150	0	0
T138	0	3	0	0
T139	383163	0	0	0
T140	153649	0	0	0
T141	52037	0	0	0
T142	8304	0	0	0
T143	5436	0	0	0
T144	209067	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1686	0	0
T51	462762	0	0	0
T70	450883	24	0	0
T72	568576	0	0	0
T97	0	1	0	0
T126	0	32	0	0
T127	0	91	0	0
T133	0	16	0	0
T158	0	220	0	0
T159	0	1	0	0
T160	0	26	0	0
T161	0	14	0	0
T162	0	21	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	2107	0	0
T51	462762	0	0	0
T70	450883	28	0	0
T72	568576	0	0	0
T101	0	3	0	0
T126	0	18	0	0
T127	0	160	0	0
T133	0	12	0	0
T158	0	218	0	0
T159	0	10	0	0
T160	0	12	0	0
T161	0	6	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0
T170	0	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1287	0	0
T51	462762	0	0	0
T70	450883	54	0	0
T72	568576	0	0	0
T97	0	2	0	0
T126	0	30	0	0
T127	0	92	0	0
T133	0	19	0	0
T158	0	206	0	0
T159	0	8	0	0
T160	0	43	0	0
T161	0	12	0	0
T162	0	15	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1414	0	0
T51	462762	0	0	0
T70	450883	46	0	0
T72	568576	0	0	0
T97	0	6	0	0
T101	0	5	0	0
T126	0	26	0	0
T127	0	75	0	0
T133	0	15	0	0
T158	0	220	0	0
T159	0	6	0	0
T160	0	29	0	0
T161	0	15	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1336	0	0
T51	462762	0	0	0
T70	450883	44	0	0
T72	568576	0	0	0
T97	0	7	0	0
T101	0	1	0	0
T126	0	13	0	0
T127	0	81	0	0
T133	0	16	0	0
T158	0	251	0	0
T159	0	9	0	0
T160	0	56	0	0
T161	0	7	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1315	0	0
T51	462762	0	0	0
T70	450883	45	0	0
T72	568576	0	0	0
T97	0	10	0	0
T126	0	16	0	0
T127	0	82	0	0
T133	0	31	0	0
T158	0	215	0	0
T159	0	8	0	0
T160	0	26	0	0
T161	0	11	0	0
T162	0	16	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1313	0	0
T51	462762	0	0	0
T70	450883	55	0	0
T72	568576	0	0	0
T97	0	2	0	0
T126	0	12	0	0
T127	0	80	0	0
T133	0	14	0	0
T158	0	243	0	0
T159	0	9	0	0
T160	0	71	0	0
T161	0	8	0	0
T162	0	20	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1311	0	0
T51	462762	0	0	0
T70	450883	48	0	0
T72	568576	0	0	0
T97	0	7	0	0
T101	0	8	0	0
T127	0	79	0	0
T133	0	13	0	0
T145	0	7	0	0
T158	0	218	0	0
T159	0	7	0	0
T160	0	33	0	0
T161	0	15	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1386	0	0
T51	462762	0	0	0
T70	450883	40	0	0
T72	568576	0	0	0
T101	0	6	0	0
T126	0	26	0	0
T127	0	82	0	0
T133	0	16	0	0
T158	0	191	0	0
T159	0	12	0	0
T160	0	57	0	0
T161	0	9	0	0
T162	0	17	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1456	0	0
T51	462762	0	0	0
T70	450883	49	0	0
T72	568576	0	0	0
T97	0	5	0	0
T101	0	7	0	0
T126	0	15	0	0
T127	0	72	0	0
T133	0	31	0	0
T158	0	221	0	0
T159	0	2	0	0
T160	0	36	0	0
T161	0	13	0	0
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T164	2535	0	0	0
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T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1347	0	0
T51	462762	0	0	0
T70	450883	55	0	0
T72	568576	0	0	0
T97	0	1	0	0
T101	0	6	0	0
T126	0	22	0	0
T127	0	61	0	0
T133	0	23	0	0
T158	0	193	0	0
T159	0	8	0	0
T160	0	43	0	0
T161	0	5	0	0
T163	712346	0	0	0
T164	2535	0	0	0
T165	4468	0	0	0
T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
T169	905248	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1415	0	0
T51	462762	0	0	0
T70	450883	52	0	0
T72	568576	0	0	0
T97	0	8	0	0
T101	0	11	0	0
T126	0	15	0	0
T127	0	80	0	0
T133	0	19	0	0
T158	0	227	0	0
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T166	2964	0	0	0
T167	958	0	0	0
T168	164155	0	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608684823	1275	0	0
T51	462762	0	0	0
T70	450883	83	0	0
T72	568576	0	0	0
T126	0	11	0	0
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T165	4468	0	0	0
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T168	164155	0	0	0
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