Line Coverage for Module :
prim_trivium
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 28 | 28 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| ALWAYS | 131 | 4 | 4 | 100.00 |
| ALWAYS | 170 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| ALWAYS | 194 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| ALWAYS | 204 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 210 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| ALWAYS | 288 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 300 | 0 | 0 | |
118
119 1/1 assign update = en_i | update_init;
Tests: T1 T2 T3
120 1/1 assign wr_en_seed = seed_req_o & seed_ack_i;
Tests: T1 T2 T3
121 1/1 assign lockup = ~(|state_q);
Tests: T1 T2 T3
122 1/1 assign err_o = lockup;
Tests: T1 T2 T3
123
124 //////////////////////////////////////////////////
125 // Regular state updating and output generation //
126 //////////////////////////////////////////////////
127
128 // The current key stream depends on the current state only.
129 if (BiviumVariant) begin : gen_update_and_output_bivium
130 always_comb begin
131 1/1 state_update = state_q;
Tests: T1 T2 T3
132 1/1 for (int unsigned i = 0; i < OutputWidth; i++) begin
Tests: T1 T2 T3
133 1/1 key_o[i] = bivium_generate_key_stream(state_update);
Tests: T1 T2 T3
134 1/1 state_update = bivium_update_state(state_update);
Tests: T1 T2 T3
135 end
136 end
137 end else begin : gen_update_and_output_trivium
138 always_comb begin
139 state_update = state_q;
140 for (int unsigned i = 0; i < OutputWidth; i++) begin
141 key_o[i] = trivium_generate_key_stream(state_update);
142 state_update = trivium_update_state(state_update);
143 end
144 end
145 end
146
147 ///////////////
148 // Reseeding //
149 ///////////////
150
151 if (SeedType == SeedTypeKeyIv) begin : gen_seed_type_key_iv
152 if (BiviumVariant) begin : gen_seed_type_key_iv_bivium
153 assign state_seed = bivium_seed_key_iv(seed_key_i, seed_iv_i);
154 end else begin : gen_seed_type_key_iv_trivium
155 assign state_seed = trivium_seed_key_iv(seed_key_i, seed_iv_i);
156 end
157
158 end else if (SeedType == SeedTypeStateFull) begin : gen_seed_type_state_full
159 assign state_seed = seed_state_full_i;
160
161 end else begin : gen_seed_type_state_partial
162 // If the primitive is idle and an update is not currently being requested (update = 1'b0), the
163 // parts not currently being reseeded remain constant, i.e., the update function above doesn't
164 // modify the state. This is required to put the primitive into a known state e.g. for known
165 // answer testing.
166 // If the primitive is busy and an update is requested, the update function always modifies
167 // the state (but the part currently being reseeded is solely determined by the new seed).
168 // Otherwise the primitive could potentially produce the same key stream output twice in a row.
169 always_comb begin
170 1/1 state_seed = !update ? state_q : state_update;
Tests: T1 T2 T3
171 // The last part may be shorter than PartialSeedWidth.
172 1/1 if (last_state_part) begin
Tests: T1 T2 T3
173 1/1 state_seed[StateWidth - 1 -: NumBitsLastPart] = seed_state_partial_i[NumBitsLastPart-1:0];
Tests: T3 T10 T9
174 end else begin
175 1/1 state_seed[state_idx_q * PartialSeedWidth +: PartialSeedWidth] = seed_state_partial_i;
Tests: T1 T2 T3
176 end
177 end
178 end
179
180 /////////////////////////////////
181 // State register and updating //
182 /////////////////////////////////
183
184 // The lockup protection can optionally be disabled at run time. This may be required to put the
185 // primitive into an all zero state, e.g., to switch off masking countermeasures for analysis if
186 // the primitive is used for generating masks. However, the err_o bit always signals this
187 // condition to the outside.
188 1/1 assign restore = lockup & (StrictLockupProtection | ~allow_lockup_i);
Tests: T1 T2 T3
189 1/1 assign state_d = restore ? StateSeed :
Tests: T1 T2 T3
190 wr_en_seed ? state_seed :
191 update ? state_update : state_q;
192
193 always_ff @(posedge clk_i or negedge rst_ni) begin : state_reg
194 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
195 1/1 state_q <= StateSeed;
Tests: T1 T2 T3
196 end else begin
197 1/1 state_q <= state_d;
Tests: T1 T2 T3
198 end
199 end
200
201 // Latch the seed enable signal and keep the request high until the last request is acknowledged.
202 1/1 assign seed_req_d = (seed_en_i | seed_req_q) & (~seed_ack_i | ~last_state_part);
Tests: T1 T2 T3
203 always_ff @(posedge clk_i or negedge rst_ni) begin : seed_req_reg
204 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
205 1/1 seed_req_q <= 1'b0;
Tests: T1 T2 T3
206 end else begin
207 1/1 seed_req_q <= seed_req_d;
Tests: T1 T2 T3
208 end
209 end
210 1/1 assign seed_req_o = seed_en_i | seed_req_q;
Tests: T1 T2 T3
211
212 if (SeedType == SeedTypeKeyIv) begin : gen_key_iv_seed_handling
213 // After receiving key and IV, the entire state needs to be updated 4 times before the key
214 // stream becomes usable. Depending on OutputWidth, a different number of initial updates are
215 // required for this. [3]
216 localparam int unsigned NumInitUpdatesFractional = (StateWidth * 4) % OutputWidth != 0 ? 1 : 0;
217 localparam int unsigned NumInitUpdates =
218 (StateWidth * 4) / OutputWidth + NumInitUpdatesFractional;
219 localparam int unsigned LastInitUpdate = NumInitUpdates - 1;
220 localparam int unsigned InitUpdatesCtrWidth = prim_util_pkg::vbits(NumInitUpdates);
221
222 logic [InitUpdatesCtrWidth-1:0] init_update_ctr_d, init_update_ctr_q;
223 logic init_update_d, init_update_q;
224 logic last_init_update;
225
226 // Count the number of initial updates done.
227 assign init_update_ctr_d = wr_en_seed ? '0 :
228 init_update_q ? init_update_ctr_q + 1'b1 : init_update_ctr_q;
229 always_ff @(posedge clk_i or negedge rst_ni) begin : init_update_ctr_reg
230 if (!rst_ni) begin
231 init_update_ctr_q <= '0;
232 end else begin
233 init_update_ctr_q <= init_update_ctr_d;
234 end
235 end
236
237 // Track whether we're currently doing the initial updates.
238 assign last_init_update = init_update_ctr_q == LastInitUpdate[InitUpdatesCtrWidth-1:0];
239 assign init_update_d = wr_en_seed ? 1'b1 :
240 last_init_update ? 1'b0 : init_update_q;
241 always_ff @(posedge clk_i or negedge rst_ni) begin : init_update_reg
242 if (!rst_ni) begin
243 init_update_q <= 1'b0;
244 end else begin
245 init_update_q <= init_update_d;
246 end
247 end
248 assign update_init = init_update_q;
249
250 // We're done after performing the initial updates.
251 assign seed_done_o = init_update_q & last_init_update;
252
253 // Tie off unused signals.
254 assign state_idx_d = '0;
255 assign state_idx_q = '0;
256 assign last_state_part = 1'b0;
257 assign unused_seed = ^{seed_state_full_i,
258 seed_state_partial_i,
259 state_idx_d,
260 state_idx_q,
261 last_state_part};
262
263 end else if (SeedType == SeedTypeStateFull) begin : gen_full_seed_handling
264
265 // Only one handshake is required.
266 assign seed_done_o = seed_req_o & seed_ack_i;
267
268 // Tie off unused signals.
269 assign update_init = 1'b0;
270 assign state_idx_d = '0;
271 assign state_idx_q = '0;
272 assign last_state_part = 1'b1;
273 assign unused_seed = ^{seed_key_i,
274 seed_iv_i,
275 seed_state_partial_i,
276 state_idx_d,
277 state_idx_q,
278 last_state_part};
279
280 end else begin : gen_partial_seed_handling
281
282 // Seed PartialSeedWidth bits of the state at a time. Track the part idx using a counter. The
283 // counter is reset when seeding the last part.
284 1/1 assign last_state_part = state_idx_q == LastStatePart[StateIdxWidth-1:0];
Tests: T1 T2 T3
285 1/1 assign state_idx_d = wr_en_seed & last_state_part ? '0 :
Tests: T1 T2 T3
286 wr_en_seed & ~last_state_part ? state_idx_q + 1'b1 : state_idx_q;
287 always_ff @(posedge clk_i or negedge rst_ni) begin : state_idx_reg
288 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
289 1/1 state_idx_q <= '0;
Tests: T1 T2 T3
290 end else begin
291 1/1 state_idx_q <= state_idx_d;
Tests: T1 T2 T3
292 end
293 end
294
295 // We're done upon receiving the last state part.
296 1/1 assign seed_done_o = seed_req_o & seed_ack_i & last_state_part;
Tests: T1 T2 T3
297
298 // Tie off unused signals.
299 assign update_init = 1'b0;
300 unreachable assign unused_seed = ^{seed_key_i,
Cond Coverage for Module :
prim_trivium
| Total | Covered | Percent |
|---|
| Conditions | 43 | 38 | 88.37 |
| Logical | 43 | 38 | 88.37 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 119
EXPRESSION (en_i | update_init)
--1- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T10,T9 |
LINE 120
EXPRESSION (seed_req_o & seed_ack_i)
-----1---- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T3,T10,T9 |
| 1 | 1 | Covered | T3,T10,T9 |
LINE 170
EXPRESSION (((!update)) ? state_q : state_update)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T10,T9 |
| 1 | Covered | T1,T2,T3 |
LINE 188
EXPRESSION (lockup & ((StrictLockupProtection | (~allow_lockup_i))))
---1-- -----------------------2----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Not Covered | |
LINE 189
EXPRESSION (restore ? StateSeed : (wr_en_seed ? state_seed : (update ? state_update : state_q)))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 189
SUB-EXPRESSION (wr_en_seed ? state_seed : (update ? state_update : state_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T10,T9 |
LINE 189
SUB-EXPRESSION (update ? state_update : state_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T10,T9 |
LINE 202
EXPRESSION ((seed_en_i | seed_req_q) & (((~seed_ack_i)) | ((~last_state_part))))
------------1----------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T10,T9 |
| 1 | 1 | Covered | T3,T10,T9 |
LINE 202
SUB-EXPRESSION (seed_en_i | seed_req_q)
----1---- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T10,T9 |
| 1 | 0 | Covered | T3,T10,T9 |
LINE 202
SUB-EXPRESSION (((~seed_ack_i)) | ((~last_state_part)))
-------1------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T10,T9 |
| 0 | 1 | Covered | T3,T10,T9 |
| 1 | 0 | Covered | T3,T10,T9 |
LINE 210
EXPRESSION (seed_en_i | seed_req_q)
----1---- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T10,T9 |
| 1 | 0 | Covered | T3,T10,T9 |
LINE 284
EXPRESSION (state_idx_q == LastStatePart[(StateIdxWidth - 1):0])
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T10,T9 |
LINE 285
EXPRESSION ((wr_en_seed & last_state_part) ? '0 : ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T10,T9 |
LINE 285
SUB-EXPRESSION (wr_en_seed & last_state_part)
-----1---- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T10,T9 |
| 1 | 0 | Covered | T3,T10,T9 |
| 1 | 1 | Covered | T3,T10,T9 |
LINE 285
SUB-EXPRESSION ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T10,T9 |
LINE 285
SUB-EXPRESSION (wr_en_seed & ((~last_state_part)))
-----1---- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T10,T9 |
LINE 296
EXPRESSION (seed_req_o & seed_ack_i & last_state_part)
-----1---- -----2---- -------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T3,T10,T9 |
| 1 | 1 | 0 | Covered | T3,T10,T9 |
| 1 | 1 | 1 | Covered | T3,T10,T9 |
Branch Coverage for Module :
prim_trivium
| Line No. | Total | Covered | Percent |
| Branches |
|
17 |
16 |
94.12 |
| TERNARY |
189 |
4 |
3 |
75.00 |
| TERNARY |
285 |
3 |
3 |
100.00 |
| IF |
194 |
2 |
2 |
100.00 |
| IF |
204 |
2 |
2 |
100.00 |
| TERNARY |
170 |
2 |
2 |
100.00 |
| IF |
172 |
2 |
2 |
100.00 |
| IF |
288 |
2 |
2 |
100.00 |
189 assign state_d = restore ? StateSeed :
-1-
==>
190 wr_en_seed ? state_seed :
-2-
==>
191 update ? state_update : state_q;
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Not Covered |
|
| 0 |
1 |
- |
Covered |
T3,T10,T9 |
| 0 |
0 |
1 |
Covered |
T3,T10,T9 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
285 assign state_idx_d = wr_en_seed & last_state_part ? '0 :
-1-
==>
286 wr_en_seed & ~last_state_part ? state_idx_q + 1'b1 : state_idx_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T3,T10,T9 |
| 0 |
1 |
Covered |
T3,T10,T9 |
| 0 |
0 |
Covered |
T1,T2,T3 |
194 if (!rst_ni) begin
-1-
195 state_q <= StateSeed;
==>
196 end else begin
197 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
204 if (!rst_ni) begin
-1-
205 seed_req_q <= 1'b0;
==>
206 end else begin
207 seed_req_q <= seed_req_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
170 state_seed = !update ? state_q : state_update;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T10,T9 |
172 if (last_state_part) begin
-1-
173 state_seed[StateWidth - 1 -: NumBitsLastPart] = seed_state_partial_i[NumBitsLastPart-1:0];
==>
174 end else begin
175 state_seed[state_idx_q * PartialSeedWidth +: PartialSeedWidth] = seed_state_partial_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T10,T9 |
| 0 |
Covered |
T1,T2,T3 |
288 if (!rst_ni) begin
-1-
289 state_idx_q <= '0;
==>
290 end else begin
291 state_idx_q <= state_idx_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_trivium
Assertion Details
PrimTriviumPartialStateSeedWhileUpdate_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
607426096 |
1272 |
0 |
0 |
| T3 |
5807 |
1 |
0 |
0 |
| T4 |
44086 |
0 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T9 |
532444 |
1 |
0 |
0 |
| T10 |
5178 |
1 |
0 |
0 |
| T11 |
0 |
1 |
0 |
0 |
| T16 |
11972 |
1 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T42 |
1758 |
0 |
0 |
0 |
| T43 |
1745 |
0 |
0 |
0 |
| T44 |
1420 |
0 |
0 |
0 |
| T45 |
8079 |
1 |
0 |
0 |
| T46 |
11347 |
1 |
0 |
0 |
| T48 |
0 |
1 |
0 |
0 |
