Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53020068	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

50195716

1

T1

303

T2

78

T3

461

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57145828	1			T1	177		T2	45		T3	391
values[0x0]	22293941	1			T1	140		T2	49		T3	244
values[0x1]	23776015	1			T1	142		T2	49		T3	223

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40773380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62442404

1

T1

334

T2

89

T3

564

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1364996	1			T1	3		T2	1		T3	3
valid_sources[0x01]	568967	1			T1	2		T2	1		T3	2
valid_sources[0x02]	343598	1			T1	2		T3	1		T4	16
valid_sources[0x03]	345080	1			T1	2		T3	3		T9	1
valid_sources[0x04]	356102	1			T1	2		T3	9		T16	1
valid_sources[0x05]	427037	1			T1	2		T3	7		T16	6
valid_sources[0x06]	470102	1			T1	1		T3	3		T9	5
valid_sources[0x07]	665769	1			T1	1		T2	1		T3	8
valid_sources[0x08]	443903	1			T1	1		T3	8		T9	2
valid_sources[0x09]	491580	1			T1	2		T3	4		T16	3
valid_sources[0x0a]	372420	1			T3	5		T16	4		T44	7
valid_sources[0x0b]	343698	1			T3	6		T9	1		T16	3
valid_sources[0x0c]	347087	1			T1	1		T3	1		T16	2
valid_sources[0x0d]	342644	1			T1	2		T2	2		T3	3
valid_sources[0x0e]	343435	1			T2	1		T3	2		T9	1
valid_sources[0x0f]	339833	1			T2	2		T3	3		T16	2
valid_sources[0x10]	340024	1			T3	2		T9	1		T16	5
valid_sources[0x11]	343196	1			T1	3		T3	3		T9	1
valid_sources[0x12]	344205	1			T1	2		T3	2		T9	2
valid_sources[0x13]	342344	1			T1	2		T3	8		T4	28
valid_sources[0x14]	345161	1			T1	2		T9	1		T16	1
valid_sources[0x15]	342273	1			T1	3		T2	1		T3	1
valid_sources[0x16]	443531	1			T1	1		T3	4		T9	2
valid_sources[0x17]	447685	1			T1	2		T3	5		T16	2
valid_sources[0x18]	341535	1			T1	1		T2	1		T16	5
valid_sources[0x19]	342280	1			T1	1		T3	4		T44	6
valid_sources[0x1a]	345410	1			T2	3		T3	2		T16	2
valid_sources[0x1b]	340056	1			T1	1		T3	3		T9	3
valid_sources[0x1c]	358642	1			T1	1		T2	1		T3	2
valid_sources[0x1d]	1157810	1			T1	5		T3	6		T9	2
valid_sources[0x1e]	342891	1			T1	3		T3	3		T16	9
valid_sources[0x1f]	992408	1			T1	1		T2	2		T3	2
valid_sources[0x20]	342265	1			T1	4		T2	2		T3	4
valid_sources[0x21]	344497	1			T1	4		T2	2		T3	4
valid_sources[0x22]	474045	1			T1	1		T3	1		T44	2
valid_sources[0x23]	350182	1			T9	3		T16	1		T4	21
valid_sources[0x24]	342723	1			T1	5		T3	2		T16	6
valid_sources[0x25]	341483	1			T1	1		T2	1		T3	3
valid_sources[0x26]	355938	1			T1	3		T16	4		T44	2
valid_sources[0x27]	342420	1			T1	2		T3	5		T16	6
valid_sources[0x28]	345092	1			T1	4		T2	2		T3	2
valid_sources[0x29]	340197	1			T1	2		T3	3		T16	2
valid_sources[0x2a]	459228	1			T1	2		T3	4		T16	5
valid_sources[0x2b]	436540	1			T9	1		T16	6		T44	5
valid_sources[0x2c]	344167	1			T1	2		T2	1		T3	3
valid_sources[0x2d]	341641	1			T3	3		T9	1		T44	1
valid_sources[0x2e]	345746	1			T1	2		T2	1		T3	5
valid_sources[0x2f]	338775	1			T1	2		T2	1		T3	3
valid_sources[0x30]	474582	1			T1	1		T2	1		T3	5
valid_sources[0x31]	343978	1			T1	4		T3	1		T9	3
valid_sources[0x32]	341204	1			T1	2		T2	1		T3	3
valid_sources[0x33]	342605	1			T1	1		T3	3		T9	3
valid_sources[0x34]	339472	1			T3	4		T9	1		T16	3
valid_sources[0x35]	341085	1			T1	2		T3	3		T9	1
valid_sources[0x36]	343707	1			T1	5		T2	1		T3	4
valid_sources[0x37]	341979	1			T1	4		T2	2		T3	4
valid_sources[0x38]	345941	1			T1	1		T2	1		T3	7
valid_sources[0x39]	372373	1			T1	2		T2	2		T3	2
valid_sources[0x3a]	340144	1			T3	5		T16	1		T44	6
valid_sources[0x3b]	390557	1			T1	4		T2	1		T3	5
valid_sources[0x3c]	466492	1			T1	1		T2	1		T3	2
valid_sources[0x3d]	343509	1			T1	4		T2	1		T3	2
valid_sources[0x3e]	344450	1			T3	2		T9	2		T16	1
valid_sources[0x3f]	560596	1			T1	3		T3	2		T44	1
valid_sources[0x40]	356020	1			T1	2		T3	4		T9	2
valid_sources[0x41]	340416	1			T3	8		T16	5		T4	15
valid_sources[0x42]	342338	1			T1	2		T3	3		T16	1
valid_sources[0x43]	506600	1			T1	1		T2	2		T3	3
valid_sources[0x44]	342713	1			T1	1		T3	4		T9	1
valid_sources[0x45]	344041	1			T1	2		T2	1		T3	4
valid_sources[0x46]	698608	1			T1	4		T2	2		T3	1
valid_sources[0x47]	361330	1			T1	1		T3	5		T9	1
valid_sources[0x48]	345766	1			T1	2		T3	3		T16	3
valid_sources[0x49]	342610	1			T3	4		T9	2		T16	1
valid_sources[0x4a]	338687	1			T1	2		T3	5		T9	1
valid_sources[0x4b]	444092	1			T1	1		T2	2		T3	4
valid_sources[0x4c]	339839	1			T1	2		T3	3		T16	3
valid_sources[0x4d]	339573	1			T1	1		T3	1		T9	1
valid_sources[0x4e]	343552	1			T1	2		T2	1		T3	2
valid_sources[0x4f]	342294	1			T1	1		T3	5		T16	3
valid_sources[0x50]	341806	1			T1	2		T2	2		T3	3
valid_sources[0x51]	447984	1			T3	1		T9	1		T16	5
valid_sources[0x52]	343630	1			T1	1		T3	4		T16	2
valid_sources[0x53]	339892	1			T2	1		T3	4		T16	3
valid_sources[0x54]	339509	1			T1	1		T2	1		T3	4
valid_sources[0x55]	343123	1			T1	3		T3	2		T16	2
valid_sources[0x56]	343277	1			T2	1		T3	2		T9	1
valid_sources[0x57]	395323	1			T1	2		T2	1		T3	4
valid_sources[0x58]	535463	1			T3	2		T43	26		T16	2
valid_sources[0x59]	343531	1			T1	1		T2	1		T3	1
valid_sources[0x5a]	343860	1			T1	1		T3	4		T9	2
valid_sources[0x5b]	342861	1			T1	2		T3	3		T16	5
valid_sources[0x5c]	344329	1			T1	2		T3	2		T16	10
valid_sources[0x5d]	345610	1			T1	1		T3	4		T16	2
valid_sources[0x5e]	344046	1			T2	2		T3	6		T16	7
valid_sources[0x5f]	394027	1			T1	3		T3	2		T16	6
valid_sources[0x60]	341482	1			T1	3		T3	4		T16	3
valid_sources[0x61]	345246	1			T1	3		T2	1		T3	3
valid_sources[0x62]	1341091	1			T3	4		T9	1		T16	10
valid_sources[0x63]	346315	1			T1	1		T2	3		T3	2
valid_sources[0x64]	343526	1			T3	2		T9	1		T16	2
valid_sources[0x65]	498291	1			T1	1		T3	4		T9	1
valid_sources[0x66]	338738	1			T1	4		T3	2		T9	3
valid_sources[0x67]	477419	1			T1	3		T3	3		T44	2
valid_sources[0x68]	344131	1			T9	1		T44	3		T4	19
valid_sources[0x69]	502082	1			T1	4		T3	4		T16	1
valid_sources[0x6a]	345568	1			T1	2		T3	4		T9	2
valid_sources[0x6b]	361779	1			T1	2		T3	8		T9	1
valid_sources[0x6c]	341329	1			T16	2		T44	3		T4	19
valid_sources[0x6d]	341877	1			T1	2		T3	2		T16	4
valid_sources[0x6e]	343480	1			T1	3		T2	1		T3	9
valid_sources[0x6f]	343991	1			T1	6		T2	1		T3	4
valid_sources[0x70]	346863	1			T1	1		T3	3		T9	1
valid_sources[0x71]	340819	1			T3	5		T9	1		T4	27
valid_sources[0x72]	346363	1			T1	1		T2	1		T3	8
valid_sources[0x73]	341490	1			T1	2		T3	1		T16	1
valid_sources[0x74]	369970	1			T1	4		T2	1		T3	3
valid_sources[0x75]	341309	1			T1	1		T3	5		T16	1
valid_sources[0x76]	344954	1			T1	1		T2	3		T3	5
valid_sources[0x77]	539224	1			T1	2		T3	3		T16	3
valid_sources[0x78]	465080	1			T1	1		T3	4		T16	5
valid_sources[0x79]	342215	1			T1	2		T2	1		T3	6
valid_sources[0x7a]	339712	1			T1	2		T2	1		T3	2
valid_sources[0x7b]	342641	1			T1	2		T3	2		T9	1
valid_sources[0x7c]	342005	1			T1	3		T3	4		T9	2
valid_sources[0x7d]	347540	1			T1	1		T3	1		T16	1
valid_sources[0x7e]	338581	1			T1	3		T3	1		T44	1
valid_sources[0x7f]	368202	1			T3	4		T4	30		T30	1
valid_sources[0x80]	502701	1			T1	2		T3	1		T16	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21951345

1

T1

80

T2

25

T3

170

values[0x0]

all_enables

biggest_size

14862293

1

T1

122

T2

27

T3

163

values[0x1]

all_enables

biggest_size

13382078

1

T1

101

T2

26

T3

128