Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

53120910

1

T1

156

T2

65

T3

397

full_word

50201878

1

T1

303

T2

78

T3

461

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	103322478	1			T1	459		T2	143		T3	858
auto[TlIntgErrCmd]	95	1			T119	3		T120	1		T121	4
auto[TlIntgErrData]	108	1			T119	12		T120	6		T121	3
auto[TlIntgErrBoth]	107	1			T119	5		T120	3		T121	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57169216

1

T1

177

T2

45

T3

391

auto[1]

46153572

1

T1

282

T2

98

T3

467

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	35215960	1			T1	97		T2	20		T3	221
auto[TlIntgErrNone]	partial	auto[1]	17904667	1			T1	59		T2	45		T3	176
auto[TlIntgErrNone]	full_word	auto[0]	21953116	1			T1	80		T2	25		T3	170
auto[TlIntgErrNone]	full_word	auto[1]	28248735	1			T1	223		T2	53		T3	291
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T119	2		T121	3		T170	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T119	1		T120	1		T121	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T170	1		T164	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T173	1		T174	1		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T119	3		T120	3		T121	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T119	7		T120	2		T121	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T119	1		T170	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T119	1		T120	1		T164	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T119	2		T120	1		T164	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T119	3		T120	2		T121	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T164	1		T165	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T170	1		T166	1		T175	1