Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	660562094	54918	0	0
RunThenComplete_M	660562094	772333	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660562094	54918	0	0
T1	7243	3	0	0
T2	2638	0	0	0
T3	12805	3	0	0
T4	225653	41	0	0
T7	30458	3	0	0
T9	3010	0	0	0
T16	7768	3	0	0
T21	0	17	0	0
T30	103985	106	0	0
T42	0	105	0	0
T43	1521	0	0	0
T44	5512	3	0	0
T47	0	145	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	660562094	772333	0	0
T1	7243	10	0	0
T2	2638	0	0	0
T3	12805	11	0	0
T4	225653	196	0	0
T7	30458	9	0	0
T9	3010	0	0	0
T16	7768	11	0	0
T21	0	74	0	0
T30	103985	256	0	0
T42	0	106	0	0
T43	1521	0	0	0
T44	5512	10	0	0
T47	0	146	0	0