Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3_done_sender	100.00	100.00				100.00	100.00
tb.dut.gen_entropy.u_entropy.u_entropy_configured	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_sha3_done_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.57	100.00	87.83		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi4False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi4False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1321124188	1320831962	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321124188	1320831962	0	0
T1	14486	14368	0	0
T2	5276	5102	0	0
T3	25610	25476	0	0
T4	451306	451142	0	0
T7	60916	60806	0	0
T9	6020	5684	0	0
T16	15536	15410	0	0
T30	207970	207842	0	0
T43	3042	2900	0	0
T44	11024	10838	0	0

Line Coverage for Instance : tb.dut.u_sha3_done_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi4False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_sha3_done_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi4False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sha3_done_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	660562094	660415981	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660562094	660415981	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi4False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi4False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	660562094	660415981	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660562094	660415981	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0