Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	661956759	64510594	0	0
DataKnown_AKnownEnable	661956759	661762681	0	0
DepthKnown_A	661956759	661762681	0	0
RvalidKnown_A	661956759	661762681	0	0
WreadyKnown_A	661956759	661762681	0	0
gen_passthru_fifo.paramCheckPass	877	877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	64510594	0	0
T1	7243	356	0	0
T2	2638	143	0	0
T3	12805	624	0	0
T4	225653	2184	0	0
T7	30458	355	0	0
T9	3010	101	0	0
T16	7768	563	0	0
T30	103985	9076	0	0
T43	1521	26	0	0
T44	5512	435	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	661956759	124357921	0	0
DataKnown_AKnownEnable	661956759	661762681	0	0
DepthKnown_A	661956759	661762681	0	0
RvalidKnown_A	661956759	661762681	0	0
WreadyKnown_A	661956759	661762681	0	0
gen_passthru_fifo.paramCheckPass	877	877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	124357921	0	0
T1	7243	1087	0	0
T2	2638	419	0	0
T3	12805	2805	0	0
T4	225653	2184	0	0
T7	30458	355	0	0
T9	3010	101	0	0
T16	7768	563	0	0
T30	103985	9076	0	0
T43	1521	26	0	0
T44	5512	435	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	661762681	0	0
T1	7243	7184	0	0
T2	2638	2551	0	0
T3	12805	12738	0	0
T4	225653	225571	0	0
T7	30458	30403	0	0
T9	3010	2842	0	0
T16	7768	7705	0	0
T30	103985	103921	0	0
T43	1521	1450	0	0
T44	5512	5419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T30	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0