Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	661956759	18566	0	0
entropy_period_rd_A	661956759	2188	0	0
intr_enable_rd_A	661956759	2921	0	0
prefix_0_rd_A	661956759	2043	0	0
prefix_10_rd_A	661956759	2050	0	0
prefix_1_rd_A	661956759	2221	0	0
prefix_2_rd_A	661956759	2253	0	0
prefix_3_rd_A	661956759	2048	0	0
prefix_4_rd_A	661956759	2152	0	0
prefix_5_rd_A	661956759	2204	0	0
prefix_6_rd_A	661956759	2168	0	0
prefix_7_rd_A	661956759	2059	0	0
prefix_8_rd_A	661956759	2147	0	0
prefix_9_rd_A	661956759	2070	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	18566	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	1349	0	0
T34	0	4716	0	0
T41	3545	0	0	0
T48	95222	827	0	0
T72	0	394	0	0
T77	258698	0	0	0
T113	1096	0	0	0
T119	0	3	0	0
T125	0	5257	0	0
T126	0	3110	0	0
T127	0	94	0	0
T128	0	28	0	0
T129	0	95	0	0
T130	114117	0	0	0
T131	254810	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2188	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	17	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	4	0	0
T113	1096	0	0	0
T119	0	63	0	0
T121	0	35	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	222	0	0
T143	0	390	0	0
T144	0	443	0	0
T145	0	5	0	0
T146	0	23	0	0
T147	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2921	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	11	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	5	0	0
T113	1096	0	0	0
T119	0	64	0	0
T122	0	6	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	223	0	0
T143	0	468	0	0
T144	0	395	0	0
T145	0	10	0	0
T146	0	13	0	0
T148	0	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2043	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	15	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	17	0	0
T113	1096	0	0	0
T119	0	36	0	0
T121	0	21	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	262	0	0
T143	0	414	0	0
T144	0	446	0	0
T145	0	3	0	0
T146	0	9	0	0
T147	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2050	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	8	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	14	0	0
T113	1096	0	0	0
T119	0	37	0	0
T122	0	8	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	235	0	0
T143	0	431	0	0
T144	0	428	0	0
T145	0	4	0	0
T146	0	8	0	0
T147	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2221	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	5	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	11	0	0
T113	1096	0	0	0
T119	0	57	0	0
T122	0	10	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	232	0	0
T143	0	387	0	0
T144	0	447	0	0
T145	0	2	0	0
T146	0	10	0	0
T147	0	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2253	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	21	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	8	0	0
T113	1096	0	0	0
T119	0	51	0	0
T121	0	16	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	232	0	0
T143	0	444	0	0
T144	0	439	0	0
T145	0	10	0	0
T146	0	7	0	0
T147	0	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2048	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	7	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	11	0	0
T113	1096	0	0	0
T119	0	61	0	0
T121	0	21	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	156	0	0
T143	0	433	0	0
T144	0	455	0	0
T145	0	7	0	0
T146	0	16	0	0
T147	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2152	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	6	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	8	0	0
T113	1096	0	0	0
T119	0	51	0	0
T122	0	7	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	187	0	0
T143	0	414	0	0
T144	0	465	0	0
T145	0	5	0	0
T146	0	9	0	0
T147	0	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2204	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	11	0	0
T41	3545	0	0	0
T48	95222	0	0	0
T77	258698	0	0	0
T103	0	8	0	0
T113	1096	0	0	0
T119	0	46	0	0
T121	0	15	0	0
T130	114117	0	0	0
T131	254810	0	0	0
T142	0	182	0	0
T143	0	459	0	0
T144	0	461	0	0
T145	0	6	0	0
T146	0	7	0	0
T147	0	1	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2168	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	10	0	0
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prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2059	0	0
T5	600171	0	0	0
T6	345597	0	0	0
T17	85215	0	0	0
T22	301662	10	0	0
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T77	258698	0	0	0
T103	0	5	0	0
T113	1096	0	0	0
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T122	0	4	0	0
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T131	254810	0	0	0
T142	0	233	0	0
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T145	0	3	0	0
T146	0	5	0	0
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prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661956759	2147	0	0
T5	600171	0	0	0
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T17	85215	0	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
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T5	600171	0	0	0
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