Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51906515	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

51520077

1

T1

324

T2

429

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56607742	1			T1	217		T2	399		T3	1
values[0x0]	22694701	1			T1	141		T2	215		T3	7
values[0x1]	24124149	1			T1	162		T2	207		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39906944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63519648

1

T1

373

T2

509

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	332318	1			T1	3		T12	2		T22	3
valid_sources[0x01]	322549	1			T1	6		T12	1		T22	39
valid_sources[0x02]	324375	1			T1	5		T22	44		T27	24
valid_sources[0x03]	535747	1			T1	4		T12	1		T22	166
valid_sources[0x04]	321649	1			T1	1		T10	1		T12	6
valid_sources[0x05]	363220	1			T1	4		T2	821		T10	1
valid_sources[0x06]	417237	1			T1	1		T12	4		T22	4
valid_sources[0x07]	324996	1			T1	6		T10	2		T12	3
valid_sources[0x08]	323498	1			T10	2		T22	5		T27	15
valid_sources[0x09]	323171	1			T1	2		T10	1		T12	3
valid_sources[0x0a]	321700	1			T1	1		T12	4		T22	2
valid_sources[0x0b]	324584	1			T1	3		T12	1		T22	33
valid_sources[0x0c]	336542	1			T10	4		T12	3		T22	3
valid_sources[0x0d]	1313903	1			T10	1		T12	6		T22	35
valid_sources[0x0e]	322841	1			T22	49		T27	23		T39	1
valid_sources[0x0f]	323700	1			T10	1		T12	3		T22	2
valid_sources[0x10]	321174	1			T1	3		T10	3		T22	2
valid_sources[0x11]	339405	1			T12	1		T22	3		T27	22
valid_sources[0x12]	417422	1			T1	2		T10	1		T12	3
valid_sources[0x13]	323921	1			T1	1		T22	63		T27	15
valid_sources[0x14]	323245	1			T1	1		T12	3		T22	3
valid_sources[0x15]	323206	1			T1	2		T7	4		T12	3
valid_sources[0x16]	325401	1			T10	1		T12	6		T22	9
valid_sources[0x17]	323297	1			T1	1		T10	3		T12	6
valid_sources[0x18]	325442	1			T1	2		T10	1		T12	4
valid_sources[0x19]	531384	1			T1	1		T12	5		T22	106
valid_sources[0x1a]	494645	1			T1	2		T12	2		T22	1
valid_sources[0x1b]	400486	1			T10	1		T12	5		T22	29
valid_sources[0x1c]	320347	1			T12	5		T22	14		T27	9
valid_sources[0x1d]	325804	1			T1	3		T12	6		T22	49
valid_sources[0x1e]	432553	1			T1	1		T10	1		T12	2
valid_sources[0x1f]	317716	1			T10	1		T12	1		T22	24
valid_sources[0x20]	459732	1			T1	3		T10	1		T12	3
valid_sources[0x21]	624290	1			T1	11		T10	1		T12	4
valid_sources[0x22]	323459	1			T1	2		T12	4		T22	33
valid_sources[0x23]	320961	1			T12	1		T22	4		T27	15
valid_sources[0x24]	322304	1			T1	3		T12	2		T22	24
valid_sources[0x25]	322981	1			T1	2		T12	4		T22	2
valid_sources[0x26]	485554	1			T10	1		T12	2		T22	2
valid_sources[0x27]	322425	1			T1	3		T10	1		T12	4
valid_sources[0x28]	322153	1			T1	6		T12	8		T22	37
valid_sources[0x29]	321062	1			T1	1		T12	3		T22	2
valid_sources[0x2a]	318184	1			T1	2		T10	1		T22	23
valid_sources[0x2b]	324619	1			T12	3		T22	3		T27	25
valid_sources[0x2c]	357563	1			T1	4		T10	2		T12	6
valid_sources[0x2d]	324604	1			T1	2		T10	1		T12	4
valid_sources[0x2e]	1367509	1			T1	4		T10	2		T12	1
valid_sources[0x2f]	327421	1			T1	6		T10	1		T12	3
valid_sources[0x30]	320424	1			T1	3		T22	10		T27	21
valid_sources[0x31]	406395	1			T1	3		T12	6		T22	43
valid_sources[0x32]	633825	1			T1	4		T12	1		T22	32
valid_sources[0x33]	321691	1			T1	2		T12	4		T22	10
valid_sources[0x34]	412265	1			T1	1		T12	2		T22	9
valid_sources[0x35]	323072	1			T1	1		T12	4		T22	15
valid_sources[0x36]	451264	1			T1	1		T10	1		T12	9
valid_sources[0x37]	322411	1			T1	1		T10	2		T12	5
valid_sources[0x38]	327743	1			T1	3		T10	1		T22	5
valid_sources[0x39]	323814	1			T1	2		T12	9		T22	1
valid_sources[0x3a]	323722	1			T1	3		T12	2		T22	7
valid_sources[0x3b]	326663	1			T1	1		T10	2		T12	2
valid_sources[0x3c]	1260927	1			T1	1		T12	2		T22	39
valid_sources[0x3d]	403820	1			T1	3		T12	5		T22	62
valid_sources[0x3e]	883889	1			T1	3		T10	1		T12	1
valid_sources[0x3f]	322385	1			T7	3		T12	1		T22	21
valid_sources[0x40]	320412	1			T1	3		T12	1		T22	4
valid_sources[0x41]	325154	1			T1	1		T12	8		T22	46
valid_sources[0x42]	457219	1			T1	2		T22	2		T27	20
valid_sources[0x43]	318327	1			T1	2		T12	10		T22	11
valid_sources[0x44]	337772	1			T1	6		T10	1		T12	1
valid_sources[0x45]	319470	1			T1	1		T12	3		T22	47
valid_sources[0x46]	324452	1			T1	2		T12	2		T22	41
valid_sources[0x47]	322730	1			T10	1		T12	3		T22	1
valid_sources[0x48]	426780	1			T1	5		T7	3		T12	4
valid_sources[0x49]	323335	1			T1	3		T7	15		T12	8
valid_sources[0x4a]	326826	1			T1	1		T12	1		T22	20
valid_sources[0x4b]	327906	1			T1	1		T12	12		T22	36
valid_sources[0x4c]	333749	1			T1	2		T12	5		T22	23
valid_sources[0x4d]	323362	1			T1	4		T12	5		T22	22
valid_sources[0x4e]	319313	1			T1	2		T12	4		T22	52
valid_sources[0x4f]	470320	1			T1	6		T12	1		T22	36
valid_sources[0x50]	323774	1			T1	1		T10	2		T12	12
valid_sources[0x51]	322079	1			T1	2		T12	4		T22	6
valid_sources[0x52]	352513	1			T1	3		T22	34		T27	25
valid_sources[0x53]	320538	1			T1	2		T10	1		T12	11
valid_sources[0x54]	322088	1			T12	2		T22	47		T27	13
valid_sources[0x55]	327774	1			T1	2		T12	4		T22	32
valid_sources[0x56]	324594	1			T12	12		T27	16		T39	1
valid_sources[0x57]	322237	1			T1	2		T12	4		T22	8
valid_sources[0x58]	322517	1			T1	2		T12	2		T22	2
valid_sources[0x59]	945478	1			T1	5		T10	1		T12	1
valid_sources[0x5a]	331101	1			T1	3		T7	2		T10	2
valid_sources[0x5b]	707313	1			T1	3		T10	1		T22	50
valid_sources[0x5c]	322863	1			T12	4		T22	3		T27	16
valid_sources[0x5d]	323817	1			T1	5		T10	2		T12	3
valid_sources[0x5e]	326549	1			T1	2		T10	1		T12	4
valid_sources[0x5f]	616649	1			T1	2		T10	1		T12	10
valid_sources[0x60]	322916	1			T10	1		T12	12		T22	7
valid_sources[0x61]	325785	1			T1	3		T12	1		T22	5
valid_sources[0x62]	402423	1			T10	1		T12	2		T22	66
valid_sources[0x63]	340886	1			T1	1		T10	1		T12	6
valid_sources[0x64]	658877	1			T1	3		T12	7		T22	68
valid_sources[0x65]	483106	1			T1	3		T12	1		T22	30
valid_sources[0x66]	320252	1			T12	3		T22	48		T27	23
valid_sources[0x67]	320837	1			T12	6		T22	6		T27	19
valid_sources[0x68]	318244	1			T1	2		T10	2		T12	2
valid_sources[0x69]	388948	1			T1	3		T12	5		T22	1
valid_sources[0x6a]	321891	1			T12	2		T22	30		T27	21
valid_sources[0x6b]	320423	1			T10	2		T12	5		T22	14
valid_sources[0x6c]	326973	1			T12	3		T22	91		T27	15
valid_sources[0x6d]	320425	1			T1	2		T12	2		T22	27
valid_sources[0x6e]	972580	1			T1	3		T12	7		T22	6
valid_sources[0x6f]	344516	1			T1	6		T12	11		T22	69
valid_sources[0x70]	509929	1			T1	4		T7	1		T10	2
valid_sources[0x71]	319206	1			T1	3		T10	2		T12	5
valid_sources[0x72]	324439	1			T1	1		T7	5		T12	1
valid_sources[0x73]	318040	1			T22	58		T27	20		T39	3
valid_sources[0x74]	326458	1			T1	10		T12	3		T22	8
valid_sources[0x75]	326247	1			T1	1		T12	3		T22	39
valid_sources[0x76]	321811	1			T1	2		T7	4		T22	3
valid_sources[0x77]	320471	1			T1	3		T12	2		T22	27
valid_sources[0x78]	350777	1			T1	2		T12	3		T22	8
valid_sources[0x79]	321944	1			T12	6		T22	6		T27	25
valid_sources[0x7a]	325594	1			T1	4		T7	2		T22	5
valid_sources[0x7b]	324854	1			T1	1		T12	2		T22	3
valid_sources[0x7c]	319711	1			T1	3		T12	9		T22	94
valid_sources[0x7d]	325294	1			T1	3		T12	3		T22	72
valid_sources[0x7e]	326928	1			T1	2		T10	1		T12	3
valid_sources[0x7f]	321633	1			T1	1		T10	1		T12	6
valid_sources[0x80]	645717	1			T1	5		T10	1		T22	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22205312

1

T1

84

T2

159

T7

2

values[0x0]

all_enables

biggest_size

15389864

1

T1

116

T2

149

T3

4

values[0x1]

all_enables

biggest_size

13924901

1

T1

124

T2

121

T3

2