Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

51990309

1

T1

196

T2

392

T3

11

full_word

51525432

1

T1

324

T2

429

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	103515421	1			T1	520		T2	821		T3	17
auto[TlIntgErrCmd]	109	1			T125	3		T126	3		T127	5
auto[TlIntgErrData]	109	1			T125	2		T126	4		T127	8
auto[TlIntgErrBoth]	102	1			T125	5		T126	3		T127	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56625923

1

T1

217

T2

399

T3

1

auto[1]

46889818

1

T1

303

T2

422

T3

16

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	34419055	1			T1	133		T2	240		T3	1
auto[TlIntgErrNone]	partial	auto[1]	17570963	1			T1	63		T2	152		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	22206721	1			T1	84		T2	159		T7	2
auto[TlIntgErrNone]	full_word	auto[1]	29318682	1			T1	240		T2	270		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T125	2		T127	2		T172	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T125	1		T126	2		T127	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T172	1		T168	2		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T126	1		T168	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T125	1		T126	2		T127	4
auto[TlIntgErrData]	partial	auto[1]	45	1			T125	1		T126	2		T127	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T176	1		T169	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T174	1		T177	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T125	3		T126	1		T127	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T125	2		T126	2		T127	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T169	2		T175	1		T178	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T173	1		T169	1		T177	1