Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : kmac_msgfifo
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 100.00 92.86 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_msgfifo 98.21 100.00 100.00 92.86 100.00



Module Instance : tb.dut.u_msgfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 100.00 92.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.43 100.00 95.83 94.52 100.00 94.23 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.76 98.75 96.74 100.00 100.00 97.06 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_msgfifo 98.72 100.00 93.62 100.00 100.00 100.00
u_packer 96.41 100.00 100.00 89.74 92.31 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : kmac_msgfifo
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN13811100.00
ALWAYS14033100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17911100.00
ALWAYS18533100.00
ALWAYS1931616100.00
CONT_ASSIGN23811100.00
ALWAYS24255100.00

137 // converted into 3-D form so the endianess here is not a problem. 138 1/1 assign fifo_wdata.data = packer_wdata; Tests: T1 T2 T3  139 always_comb begin 140 1/1 fifo_wdata.strb = '0; Tests: T1 T2 T3  141 1/1 for (int i = 0 ; i < OutWidth/8 ; i++) begin Tests: T1 T2 T3  142 1/1 fifo_wdata.strb[i] = packer_wmask[8*i]; Tests: T1 T2 T3  143 end 144 end 145 146 // MsgFIFO 147 prim_fifo_sync #( 148 .Width ($bits(fifo_t)), 149 .Pass (1'b 1), 150 .Depth (MsgDepth), 151 .Secure (EnMasking) 152 ) u_msgfifo ( 153 .clk_i, 154 .rst_ni, 155 .clr_i (prim_mubi_pkg::mubi4_test_true_strict(clear_i)), 156 157 .wvalid_i(fifo_wvalid), 158 .wready_o(fifo_wready), 159 .wdata_i (fifo_wdata), 160 161 .rvalid_o (fifo_rvalid), 162 .rready_i (fifo_rready), 163 .rdata_o (fifo_rdata), 164 165 .full_o (fifo_full_o), 166 .depth_o (fifo_depth_o), 167 .err_o (fifo_err) 168 169 ); 170 171 1/1 assign fifo_wvalid = packer_wvalid; Tests: T1 T2 T3  172 1/1 assign packer_wready = fifo_wready; Tests: T1 T2 T3  173 174 1/1 assign msg_valid_o = fifo_rvalid; Tests: T1 T2 T3  175 1/1 assign fifo_rready = msg_ready_i; Tests: T1 T2 T3  176 1/1 assign msg_data_o = fifo_rdata.data; Tests: T1 T2 T3  177 1/1 assign msg_strb_o = fifo_rdata.strb; Tests: T1 T2 T3  178 179 1/1 assign fifo_empty_o = !fifo_rvalid; Tests: T1 T2 T3  180 181 // Flush (process from outside) handling 182 flush_st_e flush_st, flush_st_d; 183 184 always_ff @(posedge clk_i or negedge rst_ni) begin 185 1/1 if (!rst_ni) begin Tests: T1 T2 T3  186 1/1 flush_st <= FlushIdle; Tests: T1 T2 T3  187 end else begin 188 1/1 flush_st <= flush_st_d; Tests: T1 T2 T3  189 end 190 end 191 192 always_comb begin 193 1/1 flush_st_d = flush_st; Tests: T1 T2 T3  194 195 1/1 msgfifo_flush_done = 1'b 0; Tests: T1 T2 T3  196 197 1/1 unique case (flush_st) Tests: T1 T2 T3  198 FlushIdle: begin 199 1/1 if (process_i) begin Tests: T1 T2 T3  200 1/1 flush_st_d = FlushPacker; Tests: T1 T2 T7  201 end else begin 202 1/1 flush_st_d = FlushIdle; Tests: T1 T2 T3  203 end 204 end 205 206 FlushPacker: begin 207 1/1 if (packer_flush_done) begin Tests: T1 T2 T7  208 1/1 flush_st_d = FlushFifo; Tests: T1 T2 T7  209 end else begin 210 1/1 flush_st_d = FlushPacker; Tests: T1 T2 T12  211 end 212 end 213 214 FlushFifo: begin 215 1/1 if (fifo_empty_o) begin Tests: T1 T2 T7  216 1/1 flush_st_d = FlushClear; Tests: T1 T2 T7  217 218 1/1 msgfifo_flush_done = 1'b 1; Tests: T1 T2 T7  219 end else begin 220 1/1 flush_st_d = FlushFifo; Tests: T1 T2 T12  221 end 222 end 223 224 FlushClear: begin 225 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin Tests: T1 T2 T7  226 1/1 flush_st_d = FlushIdle; Tests: T1 T2 T7  227 end else begin 228 1/1 flush_st_d = FlushClear; Tests: T1 T2 T7  229 end 230 end 231 232 default: begin 233 flush_st_d = FlushIdle; 234 end 235 endcase 236 end 237 238 1/1 assign process_o = msgfifo_flush_done; Tests: T1 T2 T3  239 240 // Error assign 241 always_comb begin : error_logic 242 1/1 err_o = '{ Tests: T1 T2 T3  243 valid: 1'b 0, 244 code: kmac_pkg::ErrNone, 245 info: '0 246 }; 247 248 // Priority case -> if .. else if 249 1/1 if (packer_err) begin Tests: T1 T2 T3  250 1/1 err_o = '{ Tests: T18 T34 T35  251 // If EnProtection is 0, packer_err is tied to 0 252 valid: 1'b 1, 253 code: kmac_pkg::ErrPackerIntegrity, 254 info: kmac_pkg::ErrInfoW'(flush_st) 255 }; 256 1/1 end else if (fifo_err) begin Tests: T1 T2 T3  257 1/1 err_o = '{ Tests: T18 T34 T35  258 valid: 1'b 1, 259 code: kmac_pkg::ErrMsgFifoIntegrity, 260 info: kmac_pkg::ErrInfoW'(flush_st) 261 }; 262 end MISSING_ELSE

FSM Coverage for Module : kmac_msgfifo
Summary for FSM :: flush_st
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: flush_st
statesLine No.CoveredTests
FlushClear 216 Covered T1,T2,T7
FlushFifo 208 Covered T1,T2,T7
FlushIdle 202 Covered T1,T2,T3
FlushPacker 200 Covered T1,T2,T7


transitionsLine No.CoveredTests
FlushClear->FlushIdle 226 Covered T1,T2,T7
FlushFifo->FlushClear 216 Covered T1,T2,T7
FlushIdle->FlushPacker 200 Covered T1,T2,T7
FlushPacker->FlushFifo 208 Covered T1,T2,T7



Branch Coverage for Module : kmac_msgfifo
Line No.TotalCoveredPercent
Branches 14 13 92.86
IF 185 2 2 100.00
CASE 197 9 8 88.89
IF 249 3 3 100.00


185 if (!rst_ni) begin -1- 186 flush_st <= FlushIdle; ==> 187 end else begin 188 flush_st <= flush_st_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


197 unique case (flush_st) -1- 198 FlushIdle: begin 199 if (process_i) begin -2- 200 flush_st_d = FlushPacker; ==> 201 end else begin 202 flush_st_d = FlushIdle; ==> 203 end 204 end 205 206 FlushPacker: begin 207 if (packer_flush_done) begin -3- 208 flush_st_d = FlushFifo; ==> 209 end else begin 210 flush_st_d = FlushPacker; ==> 211 end 212 end 213 214 FlushFifo: begin 215 if (fifo_empty_o) begin -4- 216 flush_st_d = FlushClear; ==> 217 218 msgfifo_flush_done = 1'b 1; 219 end else begin 220 flush_st_d = FlushFifo; ==> 221 end 222 end 223 224 FlushClear: begin 225 if (prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin -5- 226 flush_st_d = FlushIdle; ==> 227 end else begin 228 flush_st_d = FlushClear; ==> 229 end 230 end 231 232 default: begin 233 flush_st_d = FlushIdle; ==>

Branches:
-1--2--3--4--5-StatusTests
FlushIdle 1 - - - Covered T1,T2,T7
FlushIdle 0 - - - Covered T1,T2,T3
FlushPacker - 1 - - Covered T1,T2,T7
FlushPacker - 0 - - Covered T1,T2,T12
FlushFifo - - 1 - Covered T1,T2,T7
FlushFifo - - 0 - Covered T1,T2,T12
FlushClear - - - 1 Covered T1,T2,T7
FlushClear - - - 0 Covered T1,T2,T7
default - - - - Not Covered


249 if (packer_err) begin -1- 250 err_o = '{ ==> 251 // If EnProtection is 0, packer_err is tied to 0 252 valid: 1'b 1, 253 code: kmac_pkg::ErrPackerIntegrity, 254 info: kmac_pkg::ErrInfoW'(flush_st) 255 }; 256 end else if (fifo_err) begin -2- 257 err_o = '{ ==> 258 valid: 1'b 1, 259 code: kmac_pkg::ErrMsgFifoIntegrity, 260 info: kmac_pkg::ErrInfoW'(flush_st) 261 }; 262 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T18,T34,T35
0 1 Covered T18,T34,T35
0 0 Covered T1,T2,T3


Assert Coverage for Module : kmac_msgfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FlushStInValid_A 621131667 620970968 0 0
MessageValid_a 621131667 27791531 0 0
PackerDoneDelay_A 621131667 620970968 0 0
PackerDoneValid_a 621131667 56696 0 0


FlushStInValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621131667 620970968 0 0
T1 3295 3229 0 0
T2 2952 2858 0 0
T3 781 693 0 0
T7 6479 6394 0 0
T10 4028 3883 0 0
T12 9510 9458 0 0
T22 51743 51689 0 0
T27 40396 40325 0 0
T38 107016 106926 0 0
T39 5633 5565 0 0

MessageValid_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 621131667 27791531 0 0
T1 3295 56 0 0
T2 2952 125 0 0
T3 781 0 0 0
T7 6479 0 0 0
T9 0 1648 0 0
T10 4028 2 0 0
T12 9510 140 0 0
T22 51743 1076 0 0
T27 40396 576 0 0
T38 107016 814 0 0
T39 5633 132 0 0
T40 0 215 0 0

PackerDoneDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621131667 620970968 0 0
T1 3295 3229 0 0
T2 2952 2858 0 0
T3 781 693 0 0
T7 6479 6394 0 0
T10 4028 3883 0 0
T12 9510 9458 0 0
T22 51743 51689 0 0
T27 40396 40325 0 0
T38 107016 106926 0 0
T39 5633 5565 0 0

PackerDoneValid_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 621131667 56696 0 0
T1 3295 3 0 0
T2 2952 3 0 0
T3 781 0 0 0
T7 6479 1 0 0
T8 0 2 0 0
T10 4028 0 0 0
T12 9510 3 0 0
T22 51743 7 0 0
T27 40396 4 0 0
T38 107016 73 0 0
T39 5633 3 0 0
T40 0 35 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%