Unified Coverage Report :: Module :: kmac_reg_top

Module : kmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.46			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.87	100.00	99.46			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.99	99.25	96.97	100.00		98.72	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_cfg_regwen	100.00	100.00
u_cfg_shadowed0_qe	100.00	100.00				100.00
u_cfg_shadowed_en_unsupported_modestrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_fast_process	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_ready	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kmac_en	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kstrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_endianness	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_mask	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_sideload	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_state_endianness	98.66	100.00	94.64			100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_cmd	100.00	100.00
u_cmd_entropy_req	100.00	100.00
u_cmd_err_processed	100.00	100.00
u_cmd_hash_cnt_clr	100.00	100.00
u_entropy_period_prescaler	100.00	100.00	100.00			100.00
u_entropy_period_wait_timer	100.00	100.00	100.00			100.00
u_entropy_refresh_hash_cnt	62.59	77.78	50.00			60.00
u_entropy_refresh_threshold_shadowed	98.66	100.00	94.64			100.00	100.00
u_entropy_seed	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_kmac_done	100.00	100.00	100.00			100.00
u_intr_enable_kmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	62.59	77.78	50.00			60.00
u_intr_state_kmac_done	100.00	100.00	100.00			100.00
u_intr_state_kmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_kmac_done	100.00	100.00
u_intr_test_kmac_err	100.00	100.00
u_key_len	100.00	100.00	100.00			100.00
u_key_share0_0	100.00	100.00
u_key_share0_1	100.00	100.00
u_key_share0_10	100.00	100.00
u_key_share0_11	100.00	100.00
u_key_share0_12	100.00	100.00
u_key_share0_13	100.00	100.00
u_key_share0_14	100.00	100.00
u_key_share0_15	100.00	100.00
u_key_share0_2	100.00	100.00
u_key_share0_3	100.00	100.00
u_key_share0_4	100.00	100.00
u_key_share0_5	100.00	100.00
u_key_share0_6	100.00	100.00
u_key_share0_7	100.00	100.00
u_key_share0_8	100.00	100.00
u_key_share0_9	100.00	100.00
u_key_share1_0	100.00	100.00
u_key_share1_1	100.00	100.00
u_key_share1_10	100.00	100.00
u_key_share1_11	100.00	100.00
u_key_share1_12	100.00	100.00
u_key_share1_13	100.00	100.00
u_key_share1_14	100.00	100.00
u_key_share1_15	100.00	100.00
u_key_share1_2	100.00	100.00
u_key_share1_3	100.00	100.00
u_key_share1_4	100.00	100.00
u_key_share1_5	100.00	100.00
u_key_share1_6	100.00	100.00
u_key_share1_7	100.00	100.00
u_key_share1_8	100.00	100.00
u_key_share1_9	100.00	100.00
u_prefix_0	100.00	100.00	100.00			100.00
u_prefix_1	100.00	100.00	100.00			100.00
u_prefix_10	100.00	100.00	100.00			100.00
u_prefix_2	100.00	100.00	100.00			100.00
u_prefix_3	100.00	100.00	100.00			100.00
u_prefix_4	100.00	100.00	100.00			100.00
u_prefix_5	100.00	100.00	100.00			100.00
u_prefix_6	100.00	100.00	100.00			100.00
u_prefix_7	100.00	100.00	100.00			100.00
u_prefix_8	100.00	100.00	100.00			100.00
u_prefix_9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	93.69	96.05	89.53			89.19	100.00
u_status_alert_fatal_fault	100.00	100.00
u_status_alert_recov_ctrl_update_err	100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_status_sha3_absorb	100.00	100.00
u_status_sha3_idle	100.00	100.00
u_status_sha3_squeeze	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		499	499	100.00
ALWAYS	77	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
ALWAYS	136	3	3	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	774	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	885	1	1	100.00
CONT_ASSIGN	922	1	1	100.00
CONT_ASSIGN	959	1	1	100.00
CONT_ASSIGN	996	1	1	100.00
CONT_ASSIGN	1033	1	1	100.00
CONT_ASSIGN	1070	1	1	100.00
CONT_ASSIGN	1076	1	1	100.00
CONT_ASSIGN	1091	1	1	100.00
CONT_ASSIGN	1107	1	1	100.00
CONT_ASSIGN	1123	1	1	100.00
CONT_ASSIGN	1139	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1409	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1419	1	1	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1440	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1457	1	1	100.00
CONT_ASSIGN	1464	1	1	100.00
CONT_ASSIGN	1467	1	1	100.00
CONT_ASSIGN	1481	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1505	1	1	100.00
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1515	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1536	1	1	100.00
CONT_ASSIGN	1539	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1587	1	1	100.00
CONT_ASSIGN	1601	1	1	100.00
CONT_ASSIGN	1608	1	1	100.00
CONT_ASSIGN	1611	1	1	100.00
CONT_ASSIGN	1625	1	1	100.00
CONT_ASSIGN	1632	1	1	100.00
CONT_ASSIGN	1635	1	1	100.00
CONT_ASSIGN	1649	1	1	100.00
CONT_ASSIGN	1656	1	1	100.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1673	1	1	100.00
CONT_ASSIGN	1680	1	1	100.00
CONT_ASSIGN	1683	1	1	100.00
CONT_ASSIGN	1697	1	1	100.00
CONT_ASSIGN	1704	1	1	100.00
CONT_ASSIGN	1707	1	1	100.00
CONT_ASSIGN	1721	1	1	100.00
CONT_ASSIGN	1728	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1745	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1769	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1793	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1841	1	1	100.00
CONT_ASSIGN	1848	1	1	100.00
CONT_ASSIGN	1851	1	1	100.00
CONT_ASSIGN	1865	1	1	100.00
CONT_ASSIGN	1872	1	1	100.00
CONT_ASSIGN	1875	1	1	100.00
CONT_ASSIGN	1889	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1899	1	1	100.00
CONT_ASSIGN	1913	1	1	100.00
CONT_ASSIGN	1920	1	1	100.00
CONT_ASSIGN	1923	1	1	100.00
CONT_ASSIGN	1937	1	1	100.00
CONT_ASSIGN	1944	1	1	100.00
CONT_ASSIGN	1947	1	1	100.00
CONT_ASSIGN	1961	1	1	100.00
CONT_ASSIGN	1968	1	1	100.00
CONT_ASSIGN	1971	1	1	100.00
CONT_ASSIGN	1985	1	1	100.00
CONT_ASSIGN	1992	1	1	100.00
CONT_ASSIGN	1995	1	1	100.00
CONT_ASSIGN	2009	1	1	100.00
CONT_ASSIGN	2016	1	1	100.00
CONT_ASSIGN	2019	1	1	100.00
CONT_ASSIGN	2033	1	1	100.00
CONT_ASSIGN	2040	1	1	100.00
CONT_ASSIGN	2043	1	1	100.00
CONT_ASSIGN	2057	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2091	1	1	100.00
CONT_ASSIGN	2105	1	1	100.00
CONT_ASSIGN	2112	1	1	100.00
CONT_ASSIGN	2115	1	1	100.00
CONT_ASSIGN	2129	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2153	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2177	1	1	100.00
CONT_ASSIGN	2183	1	1	100.00
CONT_ASSIGN	2215	1	1	100.00
CONT_ASSIGN	2247	1	1	100.00
CONT_ASSIGN	2279	1	1	100.00
CONT_ASSIGN	2311	1	1	100.00
CONT_ASSIGN	2343	1	1	100.00
CONT_ASSIGN	2375	1	1	100.00
CONT_ASSIGN	2407	1	1	100.00
CONT_ASSIGN	2439	1	1	100.00
CONT_ASSIGN	2471	1	1	100.00
CONT_ASSIGN	2503	1	1	100.00
CONT_ASSIGN	2535	1	1	100.00
ALWAYS	2594	58	58	100.00
CONT_ASSIGN	2654	1	1	100.00
ALWAYS	2658	1	1	100.00
CONT_ASSIGN	2719	1	1	100.00
CONT_ASSIGN	2721	1	1	100.00
CONT_ASSIGN	2723	1	1	100.00
CONT_ASSIGN	2724	1	1	100.00
CONT_ASSIGN	2726	1	1	100.00
CONT_ASSIGN	2728	1	1	100.00
CONT_ASSIGN	2730	1	1	100.00
CONT_ASSIGN	2731	1	1	100.00
CONT_ASSIGN	2733	1	1	100.00
CONT_ASSIGN	2735	1	1	100.00
CONT_ASSIGN	2737	1	1	100.00
CONT_ASSIGN	2738	1	1	100.00
CONT_ASSIGN	2740	1	1	100.00
CONT_ASSIGN	2742	1	1	100.00
CONT_ASSIGN	2743	1	1	100.00
CONT_ASSIGN	2744	1	1	100.00
CONT_ASSIGN	2745	1	1	100.00
CONT_ASSIGN	2747	1	1	100.00
CONT_ASSIGN	2749	1	1	100.00
CONT_ASSIGN	2751	1	1	100.00
CONT_ASSIGN	2753	1	1	100.00
CONT_ASSIGN	2755	1	1	100.00
CONT_ASSIGN	2757	1	1	100.00
CONT_ASSIGN	2759	1	1	100.00
CONT_ASSIGN	2761	1	1	100.00
CONT_ASSIGN	2763	1	1	100.00
CONT_ASSIGN	2765	1	1	100.00
CONT_ASSIGN	2767	1	1	100.00
CONT_ASSIGN	2768	1	1	100.00
CONT_ASSIGN	2770	1	1	100.00
CONT_ASSIGN	2772	1	1	100.00
CONT_ASSIGN	2774	1	1	100.00
CONT_ASSIGN	2776	1	1	100.00
CONT_ASSIGN	2777	1	1	100.00
CONT_ASSIGN	2778	1	1	100.00
CONT_ASSIGN	2780	1	1	100.00
CONT_ASSIGN	2782	1	1	100.00
CONT_ASSIGN	2783	1	1	100.00
CONT_ASSIGN	2784	1	1	100.00
CONT_ASSIGN	2786	1	1	100.00
CONT_ASSIGN	2787	1	1	100.00
CONT_ASSIGN	2789	1	1	100.00
CONT_ASSIGN	2790	1	1	100.00
CONT_ASSIGN	2792	1	1	100.00
CONT_ASSIGN	2793	1	1	100.00
CONT_ASSIGN	2795	1	1	100.00
CONT_ASSIGN	2796	1	1	100.00
CONT_ASSIGN	2798	1	1	100.00
CONT_ASSIGN	2799	1	1	100.00
CONT_ASSIGN	2801	1	1	100.00
CONT_ASSIGN	2802	1	1	100.00
CONT_ASSIGN	2804	1	1	100.00
CONT_ASSIGN	2805	1	1	100.00
CONT_ASSIGN	2807	1	1	100.00
CONT_ASSIGN	2808	1	1	100.00
CONT_ASSIGN	2810	1	1	100.00
CONT_ASSIGN	2811	1	1	100.00
CONT_ASSIGN	2813	1	1	100.00
CONT_ASSIGN	2814	1	1	100.00
CONT_ASSIGN	2816	1	1	100.00
CONT_ASSIGN	2817	1	1	100.00
CONT_ASSIGN	2819	1	1	100.00
CONT_ASSIGN	2820	1	1	100.00
CONT_ASSIGN	2822	1	1	100.00
CONT_ASSIGN	2823	1	1	100.00
CONT_ASSIGN	2825	1	1	100.00
CONT_ASSIGN	2826	1	1	100.00
CONT_ASSIGN	2828	1	1	100.00
CONT_ASSIGN	2829	1	1	100.00
CONT_ASSIGN	2831	1	1	100.00
CONT_ASSIGN	2832	1	1	100.00
CONT_ASSIGN	2834	1	1	100.00
CONT_ASSIGN	2835	1	1	100.00
CONT_ASSIGN	2837	1	1	100.00
CONT_ASSIGN	2838	1	1	100.00
CONT_ASSIGN	2840	1	1	100.00
CONT_ASSIGN	2841	1	1	100.00
CONT_ASSIGN	2843	1	1	100.00
CONT_ASSIGN	2844	1	1	100.00
CONT_ASSIGN	2846	1	1	100.00
CONT_ASSIGN	2847	1	1	100.00
CONT_ASSIGN	2849	1	1	100.00
CONT_ASSIGN	2850	1	1	100.00
CONT_ASSIGN	2852	1	1	100.00
CONT_ASSIGN	2853	1	1	100.00
CONT_ASSIGN	2855	1	1	100.00
CONT_ASSIGN	2856	1	1	100.00
CONT_ASSIGN	2858	1	1	100.00
CONT_ASSIGN	2859	1	1	100.00
CONT_ASSIGN	2861	1	1	100.00
CONT_ASSIGN	2862	1	1	100.00
CONT_ASSIGN	2864	1	1	100.00
CONT_ASSIGN	2865	1	1	100.00
CONT_ASSIGN	2867	1	1	100.00
CONT_ASSIGN	2868	1	1	100.00
CONT_ASSIGN	2870	1	1	100.00
CONT_ASSIGN	2871	1	1	100.00
CONT_ASSIGN	2873	1	1	100.00
CONT_ASSIGN	2874	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2877	1	1	100.00
CONT_ASSIGN	2879	1	1	100.00
CONT_ASSIGN	2880	1	1	100.00
CONT_ASSIGN	2882	1	1	100.00
CONT_ASSIGN	2883	1	1	100.00
CONT_ASSIGN	2885	1	1	100.00
CONT_ASSIGN	2886	1	1	100.00
CONT_ASSIGN	2888	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2891	1	1	100.00
CONT_ASSIGN	2892	1	1	100.00
CONT_ASSIGN	2894	1	1	100.00
CONT_ASSIGN	2895	1	1	100.00
CONT_ASSIGN	2897	1	1	100.00
CONT_ASSIGN	2898	1	1	100.00
CONT_ASSIGN	2900	1	1	100.00
CONT_ASSIGN	2901	1	1	100.00
CONT_ASSIGN	2903	1	1	100.00
CONT_ASSIGN	2904	1	1	100.00
CONT_ASSIGN	2906	1	1	100.00
CONT_ASSIGN	2907	1	1	100.00
CONT_ASSIGN	2909	1	1	100.00
CONT_ASSIGN	2910	1	1	100.00
CONT_ASSIGN	2912	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2915	1	1	100.00
CONT_ASSIGN	2916	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2919	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
ALWAYS	2925	58	58	100.00
ALWAYS	2987	87	87	100.00
ALWAYS	3256	3	3	100.00
ALWAYS	3264	3	3	100.00
CONT_ASSIGN	3272	1	1	100.00
CONT_ASSIGN	3275	1	1	100.00
CONT_ASSIGN	3289	1	1	100.00
CONT_ASSIGN	3305	1	1	100.00
CONT_ASSIGN	3313	1	1	100.00
CONT_ASSIGN	3314	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : kmac_reg_top

	Total	Covered	Percent
Conditions	741	737	99.46
Logical	741	737	99.46
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
67-2658	100.00
2658-2856	98.73
2859-3272	100.00

---

Branch Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
Branches		72	72	100.00
TERNARY	2654	2	2	100.00
IF	77	3	3	100.00
TERNARY	136	3	3	100.00
IF	143	2	2	100.00
CASE	2988	58	58	100.00
IF	3256	2	2	100.00
IF	3264	2	2	100.00

2654         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

77             if (!rst_ni) begin
               -1-  
78               err_q <= '0;
                 ==>
79             end else if (intg_err || reg_we_err) begin
                        -2-  
80               err_q <= 1'b1;
                 ==>
81             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T34,T35
0	0	Covered	T1,T2,T3

136            reg_steer =
                          
137                tl_i.a_address[AW-1:0] inside {[1024:1535]} ? 2'd0 :
                                                               -1-  
                                                               ==>  
138                tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 2'd1 :
                                                               -2-  
                                                               ==>  
                                                               ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T10
0	1	Covered	T1,T2,T10
0	0	Covered	T1,T2,T3

143            if (intg_err) begin
               -1-  
144              reg_steer = 2'd2;
                 ==>
145            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T125,T126,T127
0	Covered	T1,T2,T3

2988           unique case (1'b1)
                      -1-  
2989             addr_hit[0]: begin
2990               reg_rdata_next[0] = intr_state_kmac_done_qs;
                   ==>
2991               reg_rdata_next[1] = intr_state_fifo_empty_qs;
2992               reg_rdata_next[2] = intr_state_kmac_err_qs;
2993             end
2994       
2995             addr_hit[1]: begin
2996               reg_rdata_next[0] = intr_enable_kmac_done_qs;
                   ==>
2997               reg_rdata_next[1] = intr_enable_fifo_empty_qs;
2998               reg_rdata_next[2] = intr_enable_kmac_err_qs;
2999             end
3000       
3001             addr_hit[2]: begin
3002               reg_rdata_next[0] = '0;
                   ==>
3003               reg_rdata_next[1] = '0;
3004               reg_rdata_next[2] = '0;
3005             end
3006       
3007             addr_hit[3]: begin
3008               reg_rdata_next[0] = '0;
                   ==>
3009               reg_rdata_next[1] = '0;
3010             end
3011       
3012             addr_hit[4]: begin
3013               reg_rdata_next[0] = cfg_regwen_qs;
                   ==>
3014             end
3015       
3016             addr_hit[5]: begin
3017               reg_rdata_next[0] = cfg_shadowed_kmac_en_qs;
                   ==>
3018               reg_rdata_next[3:1] = cfg_shadowed_kstrength_qs;
3019               reg_rdata_next[5:4] = cfg_shadowed_mode_qs;
3020               reg_rdata_next[8] = cfg_shadowed_msg_endianness_qs;
3021               reg_rdata_next[9] = cfg_shadowed_state_endianness_qs;
3022               reg_rdata_next[12] = cfg_shadowed_sideload_qs;
3023               reg_rdata_next[17:16] = cfg_shadowed_entropy_mode_qs;
3024               reg_rdata_next[19] = cfg_shadowed_entropy_fast_process_qs;
3025               reg_rdata_next[20] = cfg_shadowed_msg_mask_qs;
3026               reg_rdata_next[24] = cfg_shadowed_entropy_ready_qs;
3027               reg_rdata_next[26] = cfg_shadowed_en_unsupported_modestrength_qs;
3028             end
3029       
3030             addr_hit[6]: begin
3031               reg_rdata_next[5:0] = '0;
                   ==>
3032               reg_rdata_next[8] = '0;
3033               reg_rdata_next[9] = '0;
3034               reg_rdata_next[10] = '0;
3035             end
3036       
3037             addr_hit[7]: begin
3038               reg_rdata_next[0] = status_sha3_idle_qs;
                   ==>
3039               reg_rdata_next[1] = status_sha3_absorb_qs;
3040               reg_rdata_next[2] = status_sha3_squeeze_qs;
3041               reg_rdata_next[12:8] = status_fifo_depth_qs;
3042               reg_rdata_next[14] = status_fifo_empty_qs;
3043               reg_rdata_next[15] = status_fifo_full_qs;
3044               reg_rdata_next[16] = status_alert_fatal_fault_qs;
3045               reg_rdata_next[17] = status_alert_recov_ctrl_update_err_qs;
3046             end
3047       
3048             addr_hit[8]: begin
3049               reg_rdata_next[9:0] = entropy_period_prescaler_qs;
                   ==>
3050               reg_rdata_next[31:16] = entropy_period_wait_timer_qs;
3051             end
3052       
3053             addr_hit[9]: begin
3054               reg_rdata_next[9:0] = entropy_refresh_hash_cnt_qs;
                   ==>
3055             end
3056       
3057             addr_hit[10]: begin
3058               reg_rdata_next[9:0] = entropy_refresh_threshold_shadowed_qs;
                   ==>
3059             end
3060       
3061             addr_hit[11]: begin
3062               reg_rdata_next[31:0] = '0;
                   ==>
3063             end
3064       
3065             addr_hit[12]: begin
3066               reg_rdata_next[31:0] = '0;
                   ==>
3067             end
3068       
3069             addr_hit[13]: begin
3070               reg_rdata_next[31:0] = '0;
                   ==>
3071             end
3072       
3073             addr_hit[14]: begin
3074               reg_rdata_next[31:0] = '0;
                   ==>
3075             end
3076       
3077             addr_hit[15]: begin
3078               reg_rdata_next[31:0] = '0;
                   ==>
3079             end
3080       
3081             addr_hit[16]: begin
3082               reg_rdata_next[31:0] = '0;
                   ==>
3083             end
3084       
3085             addr_hit[17]: begin
3086               reg_rdata_next[31:0] = '0;
                   ==>
3087             end
3088       
3089             addr_hit[18]: begin
3090               reg_rdata_next[31:0] = '0;
                   ==>
3091             end
3092       
3093             addr_hit[19]: begin
3094               reg_rdata_next[31:0] = '0;
                   ==>
3095             end
3096       
3097             addr_hit[20]: begin
3098               reg_rdata_next[31:0] = '0;
                   ==>
3099             end
3100       
3101             addr_hit[21]: begin
3102               reg_rdata_next[31:0] = '0;
                   ==>
3103             end
3104       
3105             addr_hit[22]: begin
3106               reg_rdata_next[31:0] = '0;
                   ==>
3107             end
3108       
3109             addr_hit[23]: begin
3110               reg_rdata_next[31:0] = '0;
                   ==>
3111             end
3112       
3113             addr_hit[24]: begin
3114               reg_rdata_next[31:0] = '0;
                   ==>
3115             end
3116       
3117             addr_hit[25]: begin
3118               reg_rdata_next[31:0] = '0;
                   ==>
3119             end
3120       
3121             addr_hit[26]: begin
3122               reg_rdata_next[31:0] = '0;
                   ==>
3123             end
3124       
3125             addr_hit[27]: begin
3126               reg_rdata_next[31:0] = '0;
                   ==>
3127             end
3128       
3129             addr_hit[28]: begin
3130               reg_rdata_next[31:0] = '0;
                   ==>
3131             end
3132       
3133             addr_hit[29]: begin
3134               reg_rdata_next[31:0] = '0;
                   ==>
3135             end
3136       
3137             addr_hit[30]: begin
3138               reg_rdata_next[31:0] = '0;
                   ==>
3139             end
3140       
3141             addr_hit[31]: begin
3142               reg_rdata_next[31:0] = '0;
                   ==>
3143             end
3144       
3145             addr_hit[32]: begin
3146               reg_rdata_next[31:0] = '0;
                   ==>
3147             end
3148       
3149             addr_hit[33]: begin
3150               reg_rdata_next[31:0] = '0;
                   ==>
3151             end
3152       
3153             addr_hit[34]: begin
3154               reg_rdata_next[31:0] = '0;
                   ==>
3155             end
3156       
3157             addr_hit[35]: begin
3158               reg_rdata_next[31:0] = '0;
                   ==>
3159             end
3160       
3161             addr_hit[36]: begin
3162               reg_rdata_next[31:0] = '0;
                   ==>
3163             end
3164       
3165             addr_hit[37]: begin
3166               reg_rdata_next[31:0] = '0;
                   ==>
3167             end
3168       
3169             addr_hit[38]: begin
3170               reg_rdata_next[31:0] = '0;
                   ==>
3171             end
3172       
3173             addr_hit[39]: begin
3174               reg_rdata_next[31:0] = '0;
                   ==>
3175             end
3176       
3177             addr_hit[40]: begin
3178               reg_rdata_next[31:0] = '0;
                   ==>
3179             end
3180       
3181             addr_hit[41]: begin
3182               reg_rdata_next[31:0] = '0;
                   ==>
3183             end
3184       
3185             addr_hit[42]: begin
3186               reg_rdata_next[31:0] = '0;
                   ==>
3187             end
3188       
3189             addr_hit[43]: begin
3190               reg_rdata_next[31:0] = '0;
                   ==>
3191             end
3192       
3193             addr_hit[44]: begin
3194               reg_rdata_next[2:0] = '0;
                   ==>
3195             end
3196       
3197             addr_hit[45]: begin
3198               reg_rdata_next[31:0] = prefix_0_qs;
                   ==>
3199             end
3200       
3201             addr_hit[46]: begin
3202               reg_rdata_next[31:0] = prefix_1_qs;
                   ==>
3203             end
3204       
3205             addr_hit[47]: begin
3206               reg_rdata_next[31:0] = prefix_2_qs;
                   ==>
3207             end
3208       
3209             addr_hit[48]: begin
3210               reg_rdata_next[31:0] = prefix_3_qs;
                   ==>
3211             end
3212       
3213             addr_hit[49]: begin
3214               reg_rdata_next[31:0] = prefix_4_qs;
                   ==>
3215             end
3216       
3217             addr_hit[50]: begin
3218               reg_rdata_next[31:0] = prefix_5_qs;
                   ==>
3219             end
3220       
3221             addr_hit[51]: begin
3222               reg_rdata_next[31:0] = prefix_6_qs;
                   ==>
3223             end
3224       
3225             addr_hit[52]: begin
3226               reg_rdata_next[31:0] = prefix_7_qs;
                   ==>
3227             end
3228       
3229             addr_hit[53]: begin
3230               reg_rdata_next[31:0] = prefix_8_qs;
                   ==>
3231             end
3232       
3233             addr_hit[54]: begin
3234               reg_rdata_next[31:0] = prefix_9_qs;
                   ==>
3235             end
3236       
3237             addr_hit[55]: begin
3238               reg_rdata_next[31:0] = prefix_10_qs;
                   ==>
3239             end
3240       
3241             addr_hit[56]: begin
3242               reg_rdata_next[31:0] = err_code_qs;
                   ==>
3243             end
3244       
3245             default: begin
3246               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

3256           if (!rst_ni) begin
               -1-  
3257             rst_done <= '0;
                 ==>
3258           end else begin
3259             rst_done <= 1'b1;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

3264           if (!rst_shadowed_ni) begin
               -1-  
3265             shadow_rst_done <= '0;
                 ==>
3266           end else begin
3267             shadow_rst_done <= 1'b1;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	622478545	63177391	0	0
reAfterRv	622478545	63177391	0	0
rePulse	622478545	43197292	0	0
wePulse	622478545	19980099	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	63177391	0	0
T1	3295	416	0	0
T2	2952	600	0	0
T3	781	17	0	0
T7	6479	78	0	0
T10	4028	86	0	0
T12	9510	628	0	0
T22	51743	3919	0	0
T27	40396	2227	0	0
T38	107016	4109	0	0
T39	5633	598	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	63177391	0	0
T1	3295	416	0	0
T2	2952	600	0	0
T3	781	17	0	0
T7	6479	78	0	0
T10	4028	86	0	0
T12	9510	628	0	0
T22	51743	3919	0	0
T27	40396	2227	0	0
T38	107016	4109	0	0
T39	5633	598	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	43197292	0	0
T1	3295	169	0	0
T2	2952	303	0	0
T3	781	1	0	0
T7	6479	19	0	0
T10	4028	6	0	0
T12	9510	299	0	0
T22	51743	2469	0	0
T27	40396	1390	0	0
T38	107016	1921	0	0
T39	5633	297	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	19980099	0	0
T1	3295	247	0	0
T2	2952	297	0	0
T3	781	16	0	0
T7	6479	59	0	0
T10	4028	80	0	0
T12	9510	329	0	0
T22	51743	1450	0	0
T27	40396	837	0	0
T38	107016	2188	0	0
T39	5633	301	0	0