Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	621131667	56692	0	0
RunThenComplete_M	621131667	793783	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621131667	56692	0	0
T1	3295	3	0	0
T2	2952	3	0	0
T3	781	0	0	0
T7	6479	1	0	0
T8	0	2	0	0
T10	4028	0	0	0
T12	9510	3	0	0
T22	51743	7	0	0
T27	40396	4	0	0
T38	107016	73	0	0
T39	5633	3	0	0
T40	0	35	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	621131667	793783	0	0
T1	3295	10	0	0
T2	2952	11	0	0
T3	781	0	0	0
T7	6479	3	0	0
T8	0	6	0	0
T10	4028	0	0	0
T12	9510	11	0	0
T22	51743	39	0	0
T27	40396	24	0	0
T38	107016	74	0	0
T39	5633	11	0	0
T40	0	87	0	0