Line Coverage for Module : kmac_app
Cond Coverage for Module : kmac_app
FSM Coverage for Module : kmac_app
State, Transition and Sequence Details for FSM :: st
Branch Coverage for Module : kmac_app
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Assert Coverage for Module : kmac_app
Assertion Details
AppIntfInRange_A
SideloadKeySameToDigest_A
u_state_regs_A
Cover Directives for Properties: Details
AppIntfUseDifferentSizeKey_C
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 221 | 209 | 94.57 | |
| ALWAYS | 290 | 6 | 6 | 100.00 |
| ALWAYS | 304 | 0 | 0 | |
| ALWAYS | 304 | 4 | 4 | 100.00 |
| ALWAYS | 329 | 6 | 6 | 100.00 |
| ALWAYS | 348 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 372 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 373 | 1 | 1 | 100.00 |
| ALWAYS | 376 | 3 | 3 | 100.00 |
| ALWAYS | 385 | 3 | 3 | 100.00 |
| ALWAYS | 388 | 1 | 0 | 0.00 |
| ALWAYS | 393 | 95 | 85 | 89.47 |
| CONT_ASSIGN | 653 | 1 | 1 | 100.00 |
| ALWAYS | 659 | 3 | 3 | 100.00 |
| ALWAYS | 682 | 18 | 18 | 100.00 |
| ALWAYS | 726 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 746 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 757 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 768 | 1 | 1 | 100.00 |
| ALWAYS | 790 | 13 | 13 | 100.00 |
| ALWAYS | 815 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 839 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 839 | 1 | 1 | 100.00 |
| ALWAYS | 853 | 20 | 20 | 100.00 |
| ALWAYS | 904 | 8 | 7 | 87.50 |
| ALWAYS | 933 | 16 | 16 | 100.00 |
| ALWAYS | 960 | 3 | 3 | 100.00 |
289 always_ff @(posedge clk_i or negedge rst_ni) begin 290 2/2 if (!rst_ni) service_rejected_error <= 1'b 0; Tests: T1 T2 T3 | T1 T2 T3 291 2/2 else if (service_rejected_error_set) service_rejected_error <= 1'b 1; Tests: T1 T2 T3 | T4 T5 T6 292 2/2 else if (service_rejected_error_clr) service_rejected_error <= 1'b 0; Tests: T1 T2 T3 | T7 T8 T4 MISSING_ELSE 293 end 294 295 //////////////////////////// 296 // Application Mux/ Demux // 297 //////////////////////////// 298 299 300 // Processing return data. 301 // sends to only selected app intf. 302 // clear digest right after done to not leak info to other interface 303 always_comb begin 304 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin Tests: T1 T2 T3 305 1/1 if (i == app_id) begin Tests: T1 T2 T3 306 1/1 app_o[i] = '{ Tests: T1 T2 T3 307 ready: app_data_ready | fsm_data_ready, 308 done: app_digest_done | fsm_digest_done_q, 309 digest_share0: app_digest[0], 310 digest_share1: app_digest[1], 311 // if fsm asserts done, should be an error case. 312 error: error_i | fsm_digest_done_q | sparse_fsm_error_o 313 | service_rejected_error 314 }; 315 end else begin 316 1/1 app_o[i] = '{ Tests: T1 T2 T3 317 ready: 1'b 0, 318 done: 1'b 0, 319 digest_share0: '0, 320 digest_share1: '0, 321 error: 1'b 0 322 }; 323 end 324 end // for {i, NumAppIntf, i++} 325 end // aiways_comb 326 327 // app_id latch 328 always_ff @(posedge clk_i or negedge rst_ni) begin 329 2/2 if (!rst_ni) app_id <= AppIdxW'(0) ; // Do not select any Tests: T1 T2 T3 | T1 T2 T3 330 2/2 else if (clr_appid) app_id <= AppIdxW'(0); Tests: T1 T2 T3 | T7 T8 T9 331 2/2 else if (set_appid) app_id <= app_id_d; Tests: T1 T2 T3 | T7 T10 T8 MISSING_ELSE 332 end 333 334 // app_id selection as of now, app_id uses Priority. The assumption is that 335 // the request normally does not collide. (ROM_CTRL activates very early 336 // stage at the boot sequence) 337 // 338 // If this assumption is not true, consider RR arbiter. 339 340 // Prep for arbiter 341 logic [NumAppIntf-1:0] app_reqs; 342 logic [NumAppIntf-1:0] unused_app_gnts; 343 logic [$clog2(NumAppIntf)-1:0] arb_idx; 344 logic arb_valid; 345 logic arb_ready; 346 347 always_comb begin 348 1/1 app_reqs = '0; Tests: T7 T10 T8 349 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin Tests: T7 T10 T8 350 1/1 app_reqs[i] = app_i[i].valid; Tests: T7 T10 T8 351 end 352 end 353 354 prim_arbiter_fixed #( 355 .N (NumAppIntf), 356 .DW(1), 357 .EnDataPort(1'b 0) 358 ) u_appid_arb ( 359 .clk_i, 360 .rst_ni, 361 362 .req_i (app_reqs), 363 .data_i ('{default:'0}), 364 .gnt_o (unused_app_gnts), 365 .idx_o (arb_idx), 366 367 .valid_o (arb_valid), 368 .data_o (), // not used 369 .ready_i (arb_ready) 370 ); 371 372 1/1 assign app_id_d = AppIdxW'(arb_idx); Tests: T9 T11 T4 373 1/1 assign arb_ready = set_appid; Tests: T7 T10 T8 374 375 always_ff @(posedge clk_i or negedge rst_ni) begin 376 2/2 if (!rst_ni) fsm_digest_done_q <= 1'b 0; Tests: T1 T2 T3 | T1 T2 T3 377 1/1 else fsm_digest_done_q <= fsm_digest_done_d; Tests: T1 T2 T3 378 end 379 380 ///////// 381 // FSM // 382 ///////// 383 384 // State register385 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle) Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle): 385.1 `ifdef SIMULATION 385.2 prim_sparse_fsm_flop #( 385.3 .StateEnumT(st_e), 385.4 .Width($bits(st_e)), 385.5 .ResetValue($bits(st_e)'(StIdle)), 385.6 .EnableAlertTriggerSVA(1), 385.7 .CustomForceName("st") 385.8 ) u_state_regs ( 385.9 .clk_i ( clk_i ), 385.10 .rst_ni ( rst_ni ), 385.11 .state_i ( st_d ), 385.12 .state_o ( ) 385.13 ); 385.14 always_ff @(posedge clk_i or negedge rst_ni) begin 385.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 385.16 1/1 st <= StIdle; Tests: T1 T2 T3 385.17 end else begin 385.18 1/1 st <= st_d; Tests: T1 T2 T3 385.19 end 385.20 end 385.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o)) 385.22 else begin 385.23 `ifdef UVM 385.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 385.25 "../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv", 385, "", 1); 385.26 `else 385.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 385.28 `PRIM_STRINGIFY(u_state_regs_A)); 385.29 `endif 385.30 end 385.31 `else 385.32 prim_sparse_fsm_flop #( 385.33 .StateEnumT(st_e), 385.34 .Width($bits(st_e)), 385.35 .ResetValue($bits(st_e)'(StIdle)), 385.36 .EnableAlertTriggerSVA(1) 385.37 ) u_state_regs ( 385.38 .clk_i ( `PRIM_FLOP_CLK ), 385.39 .rst_ni ( `PRIM_FLOP_RST ), 385.40 .state_i ( st_d ), 385.41 .state_o ( st ) 385.42 ); 385.43 `endif386 387 // Create a lint error to reduce the risk of accidentally enabling this feature.
ASSERT_STATIC_LINT_ERROR(KmacSecIdleAcceptSwMsgNonDefault, SecIdleAcceptSwMsg == 0): 388.1 localparam int KmacSecIdleAcceptSwMsgNonDefault = (SecIdleAcceptSwMsg == 0) ? 1 : 2; 388.2 always_comb begin 388.3 logic unused_assert_static_lint_error; 388.4 0/1 ==> unused_assert_static_lint_error = KmacSecIdleAcceptSwMsgNonDefault'(1'b1); 388.5 end389 390 // Next State & output logic 391 // SEC_CM: FSM.SPARSE 392 always_comb begin 393 1/1 st_d = st; Tests: T1 T2 T3 394 395 1/1 mux_sel = SecIdleAcceptSwMsg ? SelSw : SelNone; Tests: T1 T2 T3 396 397 // app_id control 398 1/1 set_appid = 1'b 0; Tests: T1 T2 T3 399 1/1 clr_appid = 1'b 0; Tests: T1 T2 T3 400 401 // Commands 402 1/1 cmd_o = CmdNone; Tests: T1 T2 T3 403 404 // Software output 405 1/1 absorbed_o = prim_mubi_pkg::MuBi4False; Tests: T1 T2 T3 406 407 // Error 408 1/1 fsm_err = '{valid: 1'b 0, code: ErrNone, info: '0}; Tests: T1 T2 T3 409 1/1 sparse_fsm_error_o = 1'b 0; Tests: T1 T2 T3 410 411 1/1 clear_after_error_o = prim_mubi_pkg::MuBi4False; Tests: T1 T2 T3 412 413 1/1 service_rejected_error_set = 1'b 0; Tests: T1 T2 T3 414 1/1 service_rejected_error_clr = 1'b 0; Tests: T1 T2 T3 415 416 // If error happens, FSM asserts data ready but discard incoming msg 417 1/1 fsm_data_ready = 1'b 0; Tests: T1 T2 T3 418 1/1 fsm_digest_done_d = 1'b 0; Tests: T1 T2 T3 419 420 1/1 unique case (st) Tests: T1 T2 T3 421 StIdle: begin 422 1/1 if (arb_valid) begin Tests: T1 T2 T3 423 1/1 st_d = StAppCfg; Tests: T7 T10 T8 424 425 // choose app_id 426 1/1 set_appid = 1'b 1; Tests: T7 T10 T8 427 1/1 end else if (sw_cmd_i == CmdStart) begin Tests: T1 T2 T3 428 1/1 st_d = StSw; Tests: T1 T2 T12 429 // Software initiates the sequence 430 1/1 cmd_o = CmdStart; Tests: T1 T2 T12 431 end else begin 432 1/1 st_d = StIdle; Tests: T1 T2 T3 433 end 434 end 435 436 StAppCfg: begin 437 1/1 if (AppCfg[app_id].Mode == AppKMAC && Tests: T7 T10 T8 438 prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)) begin 439 // Check if the entropy is not configured but it is needed in 440 // `AppCfg[app_id]` (KMAC mode). 441 // 442 // SW is not properly configured, report and not request Hashing 443 // Return the app with errors 444 1/1 st_d = StError; Tests: T4 T5 T6 445 446 1/1 service_rejected_error_set = 1'b 1; Tests: T4 T5 T6 447 448 end else begin 449 // As Cfg is stable now, it sends cmd 450 1/1 st_d = StAppMsg; Tests: T7 T10 T8 451 452 // App initiates the data 453 1/1 cmd_o = CmdStart; Tests: T7 T10 T8 454 end 455 end 456 457 StAppMsg: begin 458 1/1 mux_sel = SelApp; Tests: T10 T9 T4 459 1/1 if (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last) begin Tests: T10 T9 T4 460 1/1 if (AppCfg[app_id].Mode == AppKMAC) begin Tests: T9 T4 T5 461 1/1 st_d = StAppOutLen; Tests: T9 T13 T14 462 end else begin 463 1/1 st_d = StAppProcess; Tests: T9 T4 T5 464 end 465 end else begin 466 1/1 st_d = StAppMsg; Tests: T10 T9 T4 467 end 468 end 469 470 StAppOutLen: begin 471 1/1 mux_sel = SelOutLen; Tests: T9 T13 T14 472 473 1/1 if (kmac_valid_o && kmac_ready_i) begin Tests: T9 T13 T14 474 1/1 st_d = StAppProcess; Tests: T9 T13 T14 475 end else begin 476 1/1 st_d = StAppOutLen; Tests: T13 T15 T16 477 end 478 end 479 480 StAppProcess: begin 481 1/1 cmd_o = CmdProcess; Tests: T9 T4 T5 482 1/1 st_d = StAppWait; Tests: T9 T4 T5 483 end 484 485 StAppWait: begin 486 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin Tests: T9 T4 T5 487 // Send digest to KeyMgr and complete the op 488 1/1 st_d = StIdle; Tests: T9 T4 T5 489 1/1 cmd_o = CmdDone; Tests: T9 T4 T5 490 491 1/1 clr_appid = 1'b 1; Tests: T9 T4 T5 492 end else begin 493 1/1 st_d = StAppWait; Tests: T9 T4 T5 494 end 495 end 496 497 StSw: begin 498 1/1 mux_sel = SelSw; Tests: T1 T2 T12 499 500 1/1 cmd_o = sw_cmd_i; Tests: T1 T2 T12 501 1/1 absorbed_o = absorbed_i; Tests: T1 T2 T12 502 503 1/1 if (sw_cmd_i == CmdDone) begin Tests: T1 T2 T12 504 1/1 st_d = StIdle; Tests: T1 T2 T12 505 end else begin 506 1/1 st_d = StSw; Tests: T1 T2 T12 507 end 508 end 509 510 StKeyMgrErrKeyNotValid: begin 511 1/1 st_d = StError; Tests: T7 T8 T17 512 513 // As mux_sel is not set to SelApp, app_data_ready is still 0. 514 // This logic won't accept the requests from the selected App. 515 1/1 fsm_err.valid = 1'b 1; Tests: T7 T8 T17 516 1/1 fsm_err.code = ErrKeyNotValid; Tests: T7 T8 T17 517 1/1 fsm_err.info = 24'(app_id); Tests: T7 T8 T17 518 end 519 520 StError: begin 521 // In this state, the state machine flush out the request 522 1/1 st_d = StError; Tests: T7 T8 T4 523 524 // Absorb data on the app interface. 525 1/1 fsm_data_ready = ~err_during_sw_q; Tests: T7 T8 T4 526 527 // Next step depends on two conditions: 528 // 1) Error being processed by SW 529 // 2) Last data provided from the app interface (so that the app interface is completely) 530 // drained. If the error occurred during a SW operation, the app interface is not 531 // involved, so this condition gets skipped. 532 1/1 unique case ({err_processed_i, Tests: T7 T8 T4 533 (app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q}) 534 2'b00: begin 535 // Error not processed by SW and not last data from app interface -> keep current state. 536 1/1 st_d = StError; Tests: T7 T8 T4 537 end 538 2'b01: begin 539 // Error not processed by SW but last data from app interface: 540 // 1. Send garbage digest to the app interface (in the next cycle) to complete the 541 // transaction. 542 1/1 fsm_digest_done_d = ~err_during_sw_q; Tests: T7 T8 T4 543 1/1 if (service_rejected_error) begin Tests: T7 T8 T4 544 // 2.a) Service was rejected because an app interface tried to configure KMAC while no 545 // entropy was available. It is assumed that SW is not loaded yet, so don't wait for 546 // SW to process the error. The last data from the app interface has now arrived, but 547 // we don't need to wait for the SHA3 core to have absorbed it because the data never 548 // entered the SHA3 core: the request from the app interface was terminated during the 549 // configuration phase. 550 1/1 st_d = StErrorServiceRejected; Tests: T4 T5 T6 551 end else begin 552 // 2.b) If service was not rejected, wait for SW to process the error. 553 1/1 st_d = StErrorAwaitSw; Tests: T7 T8 T17 554 end 555 end 556 2'b10: begin 557 // Error processed by SW but not last data from app interface -> wait for app interface. 558 0/1 ==> st_d = StErrorAwaitApp; 559 end 560 2'b11: begin 561 // Error processed by SW and last data from app interface: 562 // Send garbage digest to the app interface (in the next cycle) to complete the 563 // transaction. 564 0/1 ==> fsm_digest_done_d = ~err_during_sw_q; 565 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used 566 // but serves to bring the SHA3 engine back to the idle state). 567 0/1 ==> cmd_o = CmdProcess; 568 0/1 ==> st_d = StErrorWaitAbsorbed; 569 end 570 default: st_d = StError; 571 endcase 572 end 573 574 StErrorAwaitSw: begin 575 // Just wait for SW to process the error. 576 1/1 if (err_processed_i) begin Tests: T7 T8 T17 577 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used 578 // but serves to bring the SHA3 engine back to the idle state). 579 1/1 cmd_o = CmdProcess; Tests: T7 T8 T17 580 1/1 st_d = StErrorWaitAbsorbed; Tests: T7 T8 T17 581 end MISSING_ELSE 582 end 583 584 StErrorAwaitApp: begin 585 // Keep absorbing data on the app interface until the last data. 586 0/1 ==> fsm_data_ready = 1'b1; 587 0/1 ==> if (app_i[app_id].valid && app_i[app_id].last) begin 588 // Send garbage digest to the app interface (in the next cycle) to complete the 589 // transaction. 590 0/1 ==> fsm_digest_done_d = 1'b1; 591 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used 592 // but serves to bring the SHA3 engine back to the idle state). 593 0/1 ==> cmd_o = CmdProcess; 594 0/1 ==> st_d = StErrorWaitAbsorbed; 595 end ==> MISSING_ELSE 596 end 597 598 StErrorWaitAbsorbed: begin 599 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin Tests: T7 T8 T17 600 // Clear internal variables, send done command, and return to idle. 601 1/1 clr_appid = 1'b1; Tests: T7 T8 T17 602 1/1 clear_after_error_o = prim_mubi_pkg::MuBi4True; Tests: T7 T8 T17 603 1/1 service_rejected_error_clr = 1'b1; Tests: T7 T8 T17 604 1/1 cmd_o = CmdDone; Tests: T7 T8 T17 605 1/1 st_d = StIdle; Tests: T7 T8 T17 606 // If error originated from SW, report 'absorbed' to SW. 607 1/1 if (err_during_sw_q) begin Tests: T7 T8 T17 608 0/1 ==> absorbed_o = prim_mubi_pkg::MuBi4True; 609 end MISSING_ELSE 610 end MISSING_ELSE 611 end 612 613 StErrorServiceRejected: begin 614 // Clear internal variables and return to idle. 615 1/1 clr_appid = 1'b1; Tests: T4 T5 T6 616 1/1 clear_after_error_o = prim_mubi_pkg::MuBi4True; Tests: T4 T5 T6 617 1/1 service_rejected_error_clr = 1'b1; Tests: T4 T5 T6 618 1/1 st_d = StIdle; Tests: T4 T5 T6 619 end 620 621 StTerminalError: begin 622 // this state is terminal 623 1/1 st_d = st; Tests: T10 T11 T18 624 1/1 sparse_fsm_error_o = 1'b 1; Tests: T10 T11 T18 625 1/1 fsm_err.valid = 1'b 1; Tests: T10 T11 T18 626 1/1 fsm_err.code = ErrFatalError; Tests: T10 T11 T18 627 1/1 fsm_err.info = 24'(app_id); Tests: T10 T11 T18 628 end 629 630 default: begin 631 st_d = StTerminalError; 632 sparse_fsm_error_o = 1'b 1; 633 end 634 endcase 635 636 // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC 637 // Unconditionally jump into the terminal error state 638 // if the life cycle controller triggers an escalation. 639 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin Tests: T1 T2 T3 640 1/1 st_d = StTerminalError; Tests: T10 T11 T18 641 end MISSING_ELSE 642 643 // Handle errors outside the terminal error state. 644 1/1 if (st_d != StTerminalError) begin Tests: T1 T2 T3 645 // Key from keymgr is used but not valid, so abort into the invalid key error state. 646 1/1 if (keymgr_key_used && !keymgr_key_i.valid) begin Tests: T1 T2 T3 647 1/1 st_d = StKeyMgrErrKeyNotValid; Tests: T7 T8 T17 648 end MISSING_ELSE 649 end MISSING_ELSE 650 end 651 652 // Track errors occurring in SW mode. 653 1/1 assign err_during_sw_d = Tests: T1 T2 T3 654 (mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}) ? 1'b1 : // set 655 (st_d == StIdle) ? 1'b0 : // clear 656 err_during_sw_q; // hold 657 658 always_ff @(posedge clk_i or negedge rst_ni) begin 659 1/1 if (!rst_ni) begin Tests: T1 T2 T3 660 1/1 err_during_sw_q <= 1'b0; Tests: T1 T2 T3 661 end else begin 662 1/1 err_during_sw_q <= err_during_sw_d; Tests: T1 T2 T3 663 end 664 end 665 666 ////////////// 667 // Datapath // 668 ////////////// 669 670 // Encoded output length 671 assign encoded_outlen = EncodedOutLen[SelDigSize]; 672 assign encoded_outlen_mask = EncodedOutLenMask[SelKeySize]; 673 674 // Data mux 675 // This is the main part of the KeyMgr interface logic. 676 // The FSM selects KeyMgr interface in a cycle after it receives the first 677 // valid data from KeyMgr. The ready signal to the KeyMgr data interface 678 // represents the MSG_FIFO ready, only when it is in StKeyMgrMsg state. 679 // After KeyMgr sends last beat, the kmac interface (to MSG_FIFO) is switched 680 // to OutLen. OutLen is pre-defined values. See `EncodeOutLen` parameter above. 681 always_comb begin 682 1/1 app_data_ready = 1'b 0; Tests: T1 T2 T3 683 1/1 sw_ready_o = 1'b 1; Tests: T1 T2 T3 684 685 1/1 kmac_valid_o = 1'b 0; Tests: T1 T2 T3 686 1/1 kmac_data_o = '0; Tests: T1 T2 T3 687 1/1 kmac_mask_o = '0; Tests: T1 T2 T3 688 689 1/1 unique case (mux_sel_buf_kmac) Tests: T1 T2 T3 690 SelApp: begin 691 // app_id is valid at this time 692 1/1 kmac_valid_o = app_i[app_id].valid; Tests: T10 T9 T4 693 1/1 kmac_data_o = app_i[app_id].data; Tests: T10 T9 T4 694 // Expand strb to bits. prim_packer inside MSG_FIFO accepts the bit masks 695 1/1 for (int i = 0 ; i < $bits(app_i[app_id].strb) ; i++) begin Tests: T10 T9 T4 696 1/1 kmac_mask_o[8*i+:8] = {8{app_i[app_id].strb[i]}}; Tests: T10 T9 T4 697 end 698 1/1 app_data_ready = kmac_ready_i; Tests: T10 T9 T4 699 end 700 701 SelOutLen: begin 702 // Write encoded output length value 703 1/1 kmac_valid_o = 1'b 1; // always write Tests: T9 T13 T14 704 1/1 kmac_data_o = MsgWidth'(encoded_outlen); Tests: T9 T13 T14 705 1/1 kmac_mask_o = MsgWidth'(encoded_outlen_mask); Tests: T9 T13 T14 706 end 707 708 SelSw: begin 709 1/1 kmac_valid_o = sw_valid_i; Tests: T1 T2 T12 710 1/1 kmac_data_o = sw_data_i ; Tests: T1 T2 T12 711 1/1 kmac_mask_o = sw_mask_i ; Tests: T1 T2 T12 712 1/1 sw_ready_o = kmac_ready_i ; Tests: T1 T2 T12 713 end 714 715 default: begin // Incl. SelNone 716 kmac_valid_o = 1'b 0; 717 kmac_data_o = '0; 718 kmac_mask_o = '0; 719 end 720 721 endcase 722 end 723 724 // Error checking for Mux 725 always_comb begin 726 1/1 mux_err = '{valid: 1'b 0, code: ErrNone, info: '0}; Tests: T1 T2 T3 727 728 1/1 if (mux_sel_buf_err_check != SelSw && sw_valid_i) begin Tests: T1 T2 T3 729 // If SW writes message into FIFO 730 1/1 mux_err = '{ Tests: T10 T11 T18 731 valid: 1'b 1, 732 code: ErrSwPushedMsgFifo, 733 info: 24'({8'h 00, 8'(st), 8'(mux_sel_buf_err_check)}) 734 }; 735 1/1 end else if (app_active_o && sw_cmd_i != CmdNone) begin Tests: T1 T2 T3 736 // If SW issues command except start 737 1/1 mux_err = '{ Tests: T19 T20 T21 738 valid: 1'b 1, 739 code: ErrSwIssuedCmdInAppActive, 740 info: 24'(sw_cmd_i) 741 }; 742 end MISSING_ELSE 743 end 744 745 logic [AppMuxWidth-1:0] mux_sel_buf_output_logic; 746 1/1 assign mux_sel_buf_output = app_mux_sel_e'(mux_sel_buf_output_logic); Tests: T1 T2 T3 747 748 // SEC_CM: LOGIC.INTEGRITY 749 prim_sec_anchor_buf #( 750 .Width(AppMuxWidth) 751 ) u_prim_buf_state_output_sel ( 752 .in_i(mux_sel), 753 .out_o(mux_sel_buf_output_logic) 754 ); 755 756 logic [AppMuxWidth-1:0] mux_sel_buf_err_check_logic; 757 1/1 assign mux_sel_buf_err_check = app_mux_sel_e'(mux_sel_buf_err_check_logic); Tests: T1 T2 T3 758 759 // SEC_CM: LOGIC.INTEGRITY 760 prim_sec_anchor_buf #( 761 .Width(AppMuxWidth) 762 ) u_prim_buf_state_err_check ( 763 .in_i(mux_sel), 764 .out_o(mux_sel_buf_err_check_logic) 765 ); 766 767 logic [AppMuxWidth-1:0] mux_sel_buf_kmac_logic; 768 1/1 assign mux_sel_buf_kmac = app_mux_sel_e'(mux_sel_buf_kmac_logic); Tests: T1 T2 T3 769 770 // SEC_CM: LOGIC.INTEGRITY 771 prim_sec_anchor_buf #( 772 .Width(AppMuxWidth) 773 ) u_prim_buf_state_kmac_sel ( 774 .in_i(mux_sel), 775 .out_o(mux_sel_buf_kmac_logic) 776 ); 777 778 // SEC_CM: LOGIC.INTEGRITY 779 logic reg_state_valid; 780 prim_sec_anchor_buf #( 781 .Width(1) 782 ) u_prim_buf_state_output_valid ( 783 .in_i(reg_state_valid), 784 .out_o(reg_state_valid_o) 785 ); 786 787 // Keccak state Demux 788 // Keccak state --> Register output is enabled when state is in StSw 789 always_comb begin 790 1/1 reg_state_valid = 1'b 0; Tests: T1 T2 T3 791 1/1 reg_state_o = '{default:'0}; Tests: T1 T2 T3 792 1/1 if ((mux_sel_buf_output == SelSw) && Tests: T1 T2 T3 793 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin 794 1/1 reg_state_valid = keccak_state_valid_i; Tests: T1 T2 T12 795 1/1 reg_state_o = keccak_state_i; Tests: T1 T2 T12 796 // If key is sideloaded and KMAC is SW initiated 797 // hide the capacity from SW by zeroing (see #17508) 798 1/1 if (keymgr_key_en_i) begin Tests: T1 T2 T12 799 1/1 for (int i = 0; i < Share; i++) begin Tests: T22 T13 T14 800 1/1 unique case (reg_keccak_strength_i) Tests: T22 T13 T14 801 1/1 L128: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L128]] = '0; Tests: T22 T13 T14 802 1/1 L224: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L224]] = '0; Tests: T23 T24 T25 803 1/1 L256: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L256]] = '0; Tests: T13 T14 T15 804 1/1 L384: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L384]] = '0; Tests: T26 T24 T20 805 1/1 L512: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L512]] = '0; Tests: T26 T19 T24 806 default: reg_state_o[i] = '0; 807 endcase 808 end 809 end MISSING_ELSE 810 end MISSING_ELSE 811 end 812 813 // Keccak state --> KeyMgr 814 always_comb begin 815 1/1 app_digest_done = 1'b 0; Tests: T1 T2 T3 816 1/1 app_digest = '{default:'0}; Tests: T1 T2 T3 817 1/1 if (st == StAppWait && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i) && Tests: T1 T2 T3 818 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin 819 // SHA3 engine has calculated the hash. Return the data to KeyMgr 820 1/1 app_digest_done = 1'b 1; Tests: T9 T4 T5 821 822 // digest has always 2 entries. If !EnMasking, second is tied to 0. 823 1/1 for (int i = 0 ; i < Share ; i++) begin Tests: T9 T4 T5 824 // Return the portion of state. 825 1/1 app_digest[i] = keccak_state_i[i][AppDigestW-1:0]; Tests: T9 T4 T5 826 end 827 end MISSING_ELSE 828 end 829 830 831 // Secret Key Mux 832 833 // Prepare merged key if EnMasking is not set. 834 // Combine share keys into unpacked array for logic below to assign easily. 835 // SEC_CM: KEY.SIDELOAD 836 logic [MaxKeyLen-1:0] keymgr_key [Share]; 837 if (EnMasking == 1) begin : g_masked_key 838 for (genvar i = 0; i < Share; i++) begin : gen_key_pad 839 2/2 assign keymgr_key[i] = {(MaxKeyLen-KeyMgrKeyW)'(0), keymgr_key_i.key[i]}; Tests: T10 T22 T27 | T10 T22 T27 840 end 841 end else begin : g_unmasked_key 842 always_comb begin 843 keymgr_key[0] = '0; 844 for (int i = 0; i < keymgr_pkg::Shares; i++) begin 845 keymgr_key[0][KeyMgrKeyW-1:0] ^= keymgr_key_i.key[i]; 846 end 847 end 848 end 849 850 // Sideloaded key manage: Keep use sideloaded key for KMAC AppIntf until the 851 // hashing operation is finished. 852 always_comb begin 853 1/1 keymgr_key_used = 1'b0; Tests: T1 T2 T3 854 1/1 key_len_o = reg_key_len_i; Tests: T1 T2 T3 855 1/1 for (int i = 0 ; i < Share; i++) begin Tests: T1 T2 T3 856 1/1 key_data_o[i] = reg_key_data_i[i]; Tests: T1 T2 T3 857 end 858 // The key is considered invalid in all cases that are not listed below (which includes idle and 859 // error states). 860 1/1 key_valid_o = 1'b0; Tests: T1 T2 T3 861 862 1/1 unique case (st) Tests: T1 T2 T3 863 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin 864 // Key from keymgr is actually used if the current HW app interface does *keyed* MAC. 865 1/1 keymgr_key_used = AppCfg[app_id].Mode == AppKMAC; Tests: T7 T10 T8 866 1/1 key_len_o = SideloadedKey; Tests: T7 T10 T8 867 1/1 for (int i = 0 ; i < Share; i++) begin Tests: T7 T10 T8 868 1/1 key_data_o[i] = keymgr_key[i]; Tests: T7 T10 T8 869 end 870 // Key is valid if the current HW app interface does *keyed* MAC and the key provided by 871 // keymgr is valid. 872 1/1 key_valid_o = keymgr_key_used && keymgr_key_i.valid; Tests: T7 T10 T8 873 end 874 875 StSw: begin 876 1/1 if (keymgr_key_en_i) begin Tests: T1 T2 T12 877 // Key from keymgr is actually used if *keyed* MAC is enabled. 878 1/1 keymgr_key_used = kmac_en_o; Tests: T22 T13 T14 879 1/1 key_len_o = SideloadedKey; Tests: T22 T13 T14 880 1/1 for (int i = 0 ; i < Share; i++) begin Tests: T22 T13 T14 881 1/1 key_data_o[i] = keymgr_key[i]; Tests: T22 T13 T14 882 end 883 end MISSING_ELSE 884 // Key is valid if SW does *keyed* MAC and ... 885 1/1 if (kmac_en_o) begin Tests: T1 T2 T12 886 1/1 if (!keymgr_key_en_i) begin Tests: T1 T2 T12 887 // ... it uses the key from kmac's CSR, or ... 888 1/1 key_valid_o = 1'b1; Tests: T1 T2 T12 889 end else begin 890 // ... it uses the key provided by keymgr and that one is valid. 891 1/1 key_valid_o = keymgr_key_i.valid; Tests: T13 T14 T15 892 end 893 end MISSING_ELSE 894 end 895 896 default: ; 897 endcase 898 end 899 900 // Prefix Demux 901 // For SW, always prefix register. 902 // For App intf, check PrefixMode cfg and if 1, use Prefix cfg. 903 always_comb begin 904 1/1 sha3_prefix_o = '0; Tests: T1 T2 T3 905 906 1/1 unique case (st) Tests: T1 T2 T3 907 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin 908 // Check app intf cfg 909 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin Tests: T7 T10 T8 910 1/1 if (app_id == i) begin Tests: T7 T10 T8 911 1/1 if (AppCfg[i].PrefixMode == 1'b 0) begin Tests: T7 T10 T8 912 0/1 ==> sha3_prefix_o = reg_prefix_i; 913 end else begin 914 1/1 sha3_prefix_o = AppCfg[i].Prefix; Tests: T7 T10 T8 915 end 916 end MISSING_ELSE 917 end 918 end 919 920 StSw: begin 921 1/1 sha3_prefix_o = reg_prefix_i; Tests: T1 T2 T12 922 end 923 924 default: begin 925 sha3_prefix_o = reg_prefix_i; 926 end 927 endcase 928 end 929 930 // KMAC en / SHA3 mode / Strength 931 // by default, it uses reg cfg. When app intf reqs come, it uses AppCfg. 932 always_ff @(posedge clk_i or negedge rst_ni) begin 933 1/1 if (!rst_ni) begin Tests: T1 T2 T3 934 1/1 kmac_en_o <= 1'b 0; Tests: T1 T2 T3 935 1/1 sha3_mode_o <= sha3_pkg::Sha3; Tests: T1 T2 T3 936 1/1 keccak_strength_o <= sha3_pkg::L256; Tests: T1 T2 T3 937 1/1 end else if (clr_appid) begin Tests: T1 T2 T3 938 // As App completed, latch reg value 939 1/1 kmac_en_o <= reg_kmac_en_i; Tests: T7 T8 T9 940 1/1 sha3_mode_o <= reg_sha3_mode_i; Tests: T7 T8 T9 941 1/1 keccak_strength_o <= reg_keccak_strength_i; Tests: T7 T8 T9 942 1/1 end else if (set_appid) begin Tests: T1 T2 T3 943 1/1 kmac_en_o <= AppCfg[arb_idx].Mode == AppKMAC ? 1'b 1 : 1'b 0; Tests: T7 T10 T8 944 1/1 sha3_mode_o <= AppCfg[arb_idx].Mode == AppSHA3 Tests: T7 T10 T8 945 ? sha3_pkg::Sha3 : sha3_pkg::CShake; 946 1/1 keccak_strength_o <= AppCfg[arb_idx].Strength ; Tests: T7 T10 T8 947 1/1 end else if (st == StIdle) begin Tests: T1 T2 T3 948 1/1 kmac_en_o <= reg_kmac_en_i; Tests: T1 T2 T3 949 1/1 sha3_mode_o <= reg_sha3_mode_i; Tests: T1 T2 T3 950 1/1 keccak_strength_o <= reg_keccak_strength_i; Tests: T1 T2 T3 951 end MISSING_ELSE 952 end 953 954 // Status 955 assign app_active_o = (st inside {StAppCfg, StAppMsg, StAppOutLen, 956 StAppProcess, StAppWait}); 957 958 // Error Reporting ========================================================== 959 always_comb begin 960 1/1 priority casez ({fsm_err.valid, mux_err.valid}) Tests: T1 T2 T3 961 1/1 2'b ?1: error_o = mux_err; Tests: T10 T11 T18 962 1/1 2'b 10: error_o = fsm_err; Tests: T7 T10 T8 963 default: error_o = '{valid: 1'b0, code: ErrNone, info: '0};
Cond Coverage for Module : kmac_app
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 73 | 63 | 86.30 |
| Logical | 73 | 63 | 86.30 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 305
EXPRESSION (i == app_id)
------1------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 306
EXPRESSION (app_data_ready | fsm_data_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T8,T4 |
| 1 | 0 | Covered | T10,T9,T4 |
LINE 306
EXPRESSION (app_digest_done | fsm_digest_done_q)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T8,T4 |
| 1 | 0 | Covered | T9,T4,T5 |
LINE 306
EXPRESSION (error_i | fsm_digest_done_q | sparse_fsm_error_o | service_rejected_error)
---1--- --------2-------- ---------3-------- -----------4----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T4,T5,T6 |
| 0 | 0 | 1 | 0 | Covered | T10,T11,T18 |
| 0 | 1 | 0 | 0 | Covered | T7,T8,T17 |
| 1 | 0 | 0 | 0 | Covered | T14,T23,T28 |
LINE 427
EXPRESSION (sw_cmd_i == CmdStart)
-----------1----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T12 |
LINE 459
EXPRESSION (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last)
---------1--------- ---------2--------- ---------3--------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T6,T29,T30 |
| 1 | 1 | 0 | Covered | T10,T9,T4 |
| 1 | 1 | 1 | Covered | T9,T4,T5 |
LINE 460
EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
---------------------1--------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T9,T4,T5 |
| 1 | Covered | T9,T13,T14 |
LINE 473
EXPRESSION (kmac_valid_o && kmac_ready_i)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | T13,T15,T16 |
| 1 | 1 | Covered | T9,T13,T14 |
LINE 503
EXPRESSION (sw_cmd_i == CmdDone)
----------1----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T12 |
| 1 | Covered | T1,T2,T12 |
LINE 587
EXPRESSION (app_i[app_id].valid && app_i[app_id].last)
---------1--------- ---------2--------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered |
LINE 644
EXPRESSION (st_d != StTerminalError)
------------1------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T10,T11,T18 |
| 1 | Covered | T1,T2,T3 |
LINE 646
EXPRESSION (keymgr_key_used && ((!keymgr_key_i.valid)))
-------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T9,T4 |
| 1 | 1 | Covered | T7,T8,T17 |
LINE 653
EXPRESSION (((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid})) ? 1'b1 : ((st_d == StIdle) ? 1'b0 : err_during_sw_q))
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered |
LINE 653
SUB-EXPRESSION ((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}))
---------1-------- -----------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T7,T8,T4 |
| 1 | 0 | Covered | T1,T2,T12 |
| 1 | 1 | Not Covered |
LINE 653
SUB-EXPRESSION (mux_sel == SelSw)
---------1--------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T12 |
LINE 653
SUB-EXPRESSION ((st_d == StIdle) ? 1'b0 : err_during_sw_q)
--------1-------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 653
SUB-EXPRESSION (st_d == StIdle)
--------1-------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 728
EXPRESSION ((mux_sel_buf_err_check != SelSw) && sw_valid_i)
----------------1--------------- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T10,T11,T18 |
LINE 728
SUB-EXPRESSION (mux_sel_buf_err_check != SelSw)
----------------1---------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T12 |
| 1 | Covered | T1,T2,T3 |
LINE 735
EXPRESSION (app_active_o && (sw_cmd_i != CmdNone))
------1----- ----------2----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T10 |
| 1 | 0 | Covered | T7,T10,T8 |
| 1 | 1 | Covered | T19,T20,T21 |
LINE 735
SUB-EXPRESSION (sw_cmd_i != CmdNone)
----------1----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T10 |
LINE 865
EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
---------------------1--------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T9,T4,T5 |
| 1 | Covered | T7,T10,T8 |
LINE 872
EXPRESSION (keymgr_key_used && keymgr_key_i.valid)
-------1------- ---------2--------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T19,T21,T31 |
| 1 | 0 | Covered | T7,T8,T17 |
| 1 | 1 | Covered | T10,T9,T4 |
LINE 910
EXPRESSION (app_id == i)
------1------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T7,T10,T8 |
| 1 | Covered | T7,T10,T8 |
LINE 911
EXPRESSION (kmac_pkg::AppCfg[i].PrefixMode == 1'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T7,T10,T8 |
| 1 | Not Covered |
LINE 943
EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC) ? 1'b1 : 1'b0)
---------------------1---------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T9,T4,T5 |
| 1 | Covered | T7,T10,T8 |
LINE 943
SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)
---------------------1---------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T9,T4,T5 |
| 1 | Covered | T7,T10,T8 |
LINE 944
EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3) ? Sha3 : CShake)
---------------------1---------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T7,T10,T8 |
| 1 | Not Covered |
LINE 944
SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)
---------------------1---------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T7,T10,T8 |
| 1 | Not Covered |
LINE 947
EXPRESSION (st == StIdle)
-------1------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T7 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module : kmac_app
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 14 | 13 | 92.86 | (Not included in score) |
| Transitions | 45 | 20 | 44.44 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: st
| states | Line No. | Covered | Tests |
| StAppCfg | 423 | Covered | T7,T10,T8 |
| StAppMsg | 450 | Covered | T10,T9,T4 |
| StAppOutLen | 461 | Covered | T9,T13,T14 |
| StAppProcess | 463 | Covered | T9,T4,T5 |
| StAppWait | 482 | Covered | T9,T4,T5 |
| StError | 444 | Covered | T7,T8,T4 |
| StErrorAwaitApp | 558 | Not Covered | |
| StErrorAwaitSw | 553 | Covered | T7,T8,T17 |
| StErrorServiceRejected | 550 | Covered | T4,T5,T6 |
| StErrorWaitAbsorbed | 568 | Covered | T7,T8,T17 |
| StIdle | 432 | Covered | T1,T2,T3 |
| StKeyMgrErrKeyNotValid | 647 | Covered | T7,T8,T17 |
| StSw | 428 | Covered | T1,T2,T12 |
| StTerminalError | 640 | Covered | T10,T11,T18 |
| transitions | Line No. | Covered | Tests |
| StAppCfg->StAppMsg | 450 | Covered | T10,T9,T4 |
| StAppCfg->StError | 444 | Covered | T4,T5,T6 |
| StAppCfg->StKeyMgrErrKeyNotValid | 647 | Covered | T7,T8,T17 |
| StAppCfg->StTerminalError | 640 | Not Covered | |
| StAppMsg->StAppOutLen | 461 | Covered | T9,T13,T14 |
| StAppMsg->StAppProcess | 463 | Covered | T9,T4,T5 |
| StAppMsg->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StAppMsg->StTerminalError | 640 | Covered | T10,T32,T33 |
| StAppOutLen->StAppProcess | 474 | Covered | T9,T13,T14 |
| StAppOutLen->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StAppOutLen->StTerminalError | 640 | Not Covered | |
| StAppProcess->StAppWait | 482 | Covered | T9,T4,T5 |
| StAppProcess->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StAppProcess->StTerminalError | 640 | Not Covered | |
| StAppWait->StIdle | 488 | Covered | T9,T4,T5 |
| StAppWait->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StAppWait->StTerminalError | 640 | Not Covered | |
| StError->StErrorAwaitApp | 558 | Not Covered | |
| StError->StErrorAwaitSw | 553 | Covered | T7,T8,T17 |
| StError->StErrorServiceRejected | 550 | Covered | T4,T5,T6 |
| StError->StErrorWaitAbsorbed | 568 | Not Covered | |
| StError->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StError->StTerminalError | 640 | Not Covered | |
| StErrorAwaitApp->StErrorWaitAbsorbed | 594 | Not Covered | |
| StErrorAwaitApp->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StErrorAwaitApp->StTerminalError | 640 | Not Covered | |
| StErrorAwaitSw->StErrorWaitAbsorbed | 580 | Covered | T7,T8,T17 |
| StErrorAwaitSw->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StErrorAwaitSw->StTerminalError | 640 | Not Covered | |
| StErrorServiceRejected->StIdle | 618 | Covered | T4,T5,T6 |
| StErrorServiceRejected->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StErrorServiceRejected->StTerminalError | 640 | Not Covered | |
| StErrorWaitAbsorbed->StIdle | 605 | Covered | T7,T8,T17 |
| StErrorWaitAbsorbed->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StErrorWaitAbsorbed->StTerminalError | 640 | Not Covered | |
| StIdle->StAppCfg | 423 | Covered | T7,T10,T8 |
| StIdle->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StIdle->StSw | 428 | Covered | T1,T2,T12 |
| StIdle->StTerminalError | 640 | Covered | T18,T34,T35 |
| StKeyMgrErrKeyNotValid->StError | 511 | Covered | T7,T8,T17 |
| StKeyMgrErrKeyNotValid->StTerminalError | 640 | Not Covered | |
| StSw->StIdle | 504 | Covered | T1,T2,T12 |
| StSw->StKeyMgrErrKeyNotValid | 647 | Not Covered | |
| StSw->StTerminalError | 640 | Covered | T11,T36,T37 |
| StTerminalError->StKeyMgrErrKeyNotValid | 647 | Not Covered |
Branch Coverage for Module : kmac_app
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 89 | 81 | 91.01 | |
| TERNARY | 653 | 3 | 2 | 66.67 |
| IF | 290 | 4 | 4 | 100.00 |
| IF | 305 | 2 | 2 | 100.00 |
| IF | 329 | 4 | 4 | 100.00 |
| IF | 376 | 2 | 2 | 100.00 |
| IF | 385 | 2 | 2 | 100.00 |
| CASE | 420 | 32 | 26 | 81.25 |
| IF | 639 | 2 | 2 | 100.00 |
| IF | 644 | 3 | 3 | 100.00 |
| IF | 659 | 2 | 2 | 100.00 |
| CASE | 689 | 4 | 4 | 100.00 |
| IF | 728 | 3 | 3 | 100.00 |
| IF | 792 | 3 | 3 | 100.00 |
| IF | 817 | 2 | 2 | 100.00 |
| CASE | 862 | 7 | 7 | 100.00 |
| CASE | 906 | 3 | 3 | 100.00 |
| IF | 933 | 8 | 7 | 87.50 |
| CASE | 960 | 3 | 3 | 100.00 |
653 assign err_during_sw_d = 654 (mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}) ? 1'b1 : // set -1- ==> 655 (st_d == StIdle) ? 1'b0 : // clear -2- ==> ==>
Branches:
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 1 | - | Not Covered | |
| 0 | 1 | Covered | T1,T2,T3 |
| 0 | 0 | Covered | T1,T2,T7 |
290 if (!rst_ni) service_rejected_error <= 1'b 0; -1- ==> 291 else if (service_rejected_error_set) service_rejected_error <= 1'b 1; -2- ==> 292 else if (service_rejected_error_clr) service_rejected_error <= 1'b 0; -3- ==> MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 1 | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | Covered | T4,T5,T6 |
| 0 | 0 | 1 | Covered | T7,T8,T4 |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
305 if (i == app_id) begin -1- 306 app_o[i] = '{ ==> 307 ready: app_data_ready | fsm_data_ready, 308 done: app_digest_done | fsm_digest_done_q, 309 digest_share0: app_digest[0], 310 digest_share1: app_digest[1], 311 // if fsm asserts done, should be an error case. 312 error: error_i | fsm_digest_done_q | sparse_fsm_error_o 313 | service_rejected_error 314 }; 315 end else begin 316 app_o[i] = '{ ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
329 if (!rst_ni) app_id <= AppIdxW'(0) ; // Do not select any -1- ==> 330 else if (clr_appid) app_id <= AppIdxW'(0); -2- ==> 331 else if (set_appid) app_id <= app_id_d; -3- ==> MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 1 | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | Covered | T7,T8,T9 |
| 0 | 0 | 1 | Covered | T7,T10,T8 |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
376 if (!rst_ni) fsm_digest_done_q <= 1'b 0; -1- ==> 377 else fsm_digest_done_q <= fsm_digest_done_d; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
385 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
420 unique case (st) -1- 421 StIdle: begin 422 if (arb_valid) begin -2- 423 st_d = StAppCfg; ==> 424 425 // choose app_id 426 set_appid = 1'b 1; 427 end else if (sw_cmd_i == CmdStart) begin -3- 428 st_d = StSw; ==> 429 // Software initiates the sequence 430 cmd_o = CmdStart; 431 end else begin 432 st_d = StIdle; ==> 433 end 434 end 435 436 StAppCfg: begin 437 if (AppCfg[app_id].Mode == AppKMAC && -4- 438 prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)) begin 439 // Check if the entropy is not configured but it is needed in 440 // `AppCfg[app_id]` (KMAC mode). 441 // 442 // SW is not properly configured, report and not request Hashing 443 // Return the app with errors 444 st_d = StError; ==> 445 446 service_rejected_error_set = 1'b 1; 447 448 end else begin 449 // As Cfg is stable now, it sends cmd 450 st_d = StAppMsg; ==> 451 452 // App initiates the data 453 cmd_o = CmdStart; 454 end 455 end 456 457 StAppMsg: begin 458 mux_sel = SelApp; 459 if (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last) begin -5- 460 if (AppCfg[app_id].Mode == AppKMAC) begin -6- 461 st_d = StAppOutLen; ==> 462 end else begin 463 st_d = StAppProcess; ==> 464 end 465 end else begin 466 st_d = StAppMsg; ==> 467 end 468 end 469 470 StAppOutLen: begin 471 mux_sel = SelOutLen; 472 473 if (kmac_valid_o && kmac_ready_i) begin -7- 474 st_d = StAppProcess; ==> 475 end else begin 476 st_d = StAppOutLen; ==> 477 end 478 end 479 480 StAppProcess: begin 481 cmd_o = CmdProcess; ==> 482 st_d = StAppWait; 483 end 484 485 StAppWait: begin 486 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin -8- 487 // Send digest to KeyMgr and complete the op 488 st_d = StIdle; ==> 489 cmd_o = CmdDone; 490 491 clr_appid = 1'b 1; 492 end else begin 493 st_d = StAppWait; ==> 494 end 495 end 496 497 StSw: begin 498 mux_sel = SelSw; 499 500 cmd_o = sw_cmd_i; 501 absorbed_o = absorbed_i; 502 503 if (sw_cmd_i == CmdDone) begin -9- 504 st_d = StIdle; ==> 505 end else begin 506 st_d = StSw; ==> 507 end 508 end 509 510 StKeyMgrErrKeyNotValid: begin 511 st_d = StError; ==> 512 513 // As mux_sel is not set to SelApp, app_data_ready is still 0. 514 // This logic won't accept the requests from the selected App. 515 fsm_err.valid = 1'b 1; 516 fsm_err.code = ErrKeyNotValid; 517 fsm_err.info = 24'(app_id); 518 end 519 520 StError: begin 521 // In this state, the state machine flush out the request 522 st_d = StError; 523 524 // Absorb data on the app interface. 525 fsm_data_ready = ~err_during_sw_q; 526 527 // Next step depends on two conditions: 528 // 1) Error being processed by SW 529 // 2) Last data provided from the app interface (so that the app interface is completely) 530 // drained. If the error occurred during a SW operation, the app interface is not 531 // involved, so this condition gets skipped. 532 unique case ({err_processed_i, -10- 533 (app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q}) 534 2'b00: begin 535 // Error not processed by SW and not last data from app interface -> keep current state. 536 st_d = StError; ==> 537 end 538 2'b01: begin 539 // Error not processed by SW but last data from app interface: 540 // 1. Send garbage digest to the app interface (in the next cycle) to complete the 541 // transaction. 542 fsm_digest_done_d = ~err_during_sw_q; 543 if (service_rejected_error) begin -11- 544 // 2.a) Service was rejected because an app interface tried to configure KMAC while no 545 // entropy was available. It is assumed that SW is not loaded yet, so don't wait for 546 // SW to process the error. The last data from the app interface has now arrived, but 547 // we don't need to wait for the SHA3 core to have absorbed it because the data never 548 // entered the SHA3 core: the request from the app interface was terminated during the 549 // configuration phase. 550 st_d = StErrorServiceRejected; ==> 551 end else begin 552 // 2.b) If service was not rejected, wait for SW to process the error. 553 st_d = StErrorAwaitSw; ==> 554 end 555 end 556 2'b10: begin 557 // Error processed by SW but not last data from app interface -> wait for app interface. 558 st_d = StErrorAwaitApp; ==> 559 end 560 2'b11: begin 561 // Error processed by SW and last data from app interface: 562 // Send garbage digest to the app interface (in the next cycle) to complete the 563 // transaction. 564 fsm_digest_done_d = ~err_during_sw_q; ==> 565 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used 566 // but serves to bring the SHA3 engine back to the idle state). 567 cmd_o = CmdProcess; 568 st_d = StErrorWaitAbsorbed; 569 end 570 default: st_d = StError; ==> 571 endcase 572 end 573 574 StErrorAwaitSw: begin 575 // Just wait for SW to process the error. 576 if (err_processed_i) begin -12- 577 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used 578 // but serves to bring the SHA3 engine back to the idle state). 579 cmd_o = CmdProcess; ==> 580 st_d = StErrorWaitAbsorbed; 581 end MISSING_ELSE ==> 582 end 583 584 StErrorAwaitApp: begin 585 // Keep absorbing data on the app interface until the last data. 586 fsm_data_ready = 1'b1; 587 if (app_i[app_id].valid && app_i[app_id].last) begin -13- 588 // Send garbage digest to the app interface (in the next cycle) to complete the 589 // transaction. 590 fsm_digest_done_d = 1'b1; ==> 591 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used 592 // but serves to bring the SHA3 engine back to the idle state). 593 cmd_o = CmdProcess; 594 st_d = StErrorWaitAbsorbed; 595 end MISSING_ELSE ==> 596 end 597 598 StErrorWaitAbsorbed: begin 599 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin -14- 600 // Clear internal variables, send done command, and return to idle. 601 clr_appid = 1'b1; 602 clear_after_error_o = prim_mubi_pkg::MuBi4True; 603 service_rejected_error_clr = 1'b1; 604 cmd_o = CmdDone; 605 st_d = StIdle; 606 // If error originated from SW, report 'absorbed' to SW. 607 if (err_during_sw_q) begin -15- 608 absorbed_o = prim_mubi_pkg::MuBi4True; ==> 609 end MISSING_ELSE ==> 610 end MISSING_ELSE ==> 611 end 612 613 StErrorServiceRejected: begin 614 // Clear internal variables and return to idle. 615 clr_appid = 1'b1; ==> 616 clear_after_error_o = prim_mubi_pkg::MuBi4True; 617 service_rejected_error_clr = 1'b1; 618 st_d = StIdle; 619 end 620 621 StTerminalError: begin 622 // this state is terminal 623 st_d = st; ==> 624 sparse_fsm_error_o = 1'b 1; 625 fsm_err.valid = 1'b 1; 626 fsm_err.code = ErrFatalError; 627 fsm_err.info = 24'(app_id); 628 end 629 630 default: begin 631 st_d = StTerminalError; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| StIdle | 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T7,T10,T8 |
| StIdle | 0 | 1 | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T12 |
| StIdle | 0 | 0 | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| StAppCfg | - | - | 1 | - | - | - | - | - | - | - | - | - | - | - | Covered | T4,T5,T6 |
| StAppCfg | - | - | 0 | - | - | - | - | - | - | - | - | - | - | - | Covered | T7,T10,T8 |
| StAppMsg | - | - | - | 1 | 1 | - | - | - | - | - | - | - | - | - | Covered | T9,T13,T14 |
| StAppMsg | - | - | - | 1 | 0 | - | - | - | - | - | - | - | - | - | Covered | T9,T4,T5 |
| StAppMsg | - | - | - | 0 | - | - | - | - | - | - | - | - | - | - | Covered | T10,T9,T4 |
| StAppOutLen | - | - | - | - | - | 1 | - | - | - | - | - | - | - | - | Covered | T9,T13,T14 |
| StAppOutLen | - | - | - | - | - | 0 | - | - | - | - | - | - | - | - | Covered | T13,T15,T16 |
| StAppProcess | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T9,T4,T5 |
| StAppWait | - | - | - | - | - | - | 1 | - | - | - | - | - | - | - | Covered | T9,T4,T5 |
| StAppWait | - | - | - | - | - | - | 0 | - | - | - | - | - | - | - | Covered | T9,T4,T5 |
| StSw | - | - | - | - | - | - | - | 1 | - | - | - | - | - | - | Covered | T1,T2,T12 |
| StSw | - | - | - | - | - | - | - | 0 | - | - | - | - | - | - | Covered | T1,T2,T12 |
| StKeyMgrErrKeyNotValid | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T7,T8,T17 |
| StError | - | - | - | - | - | - | - | - | 2'b00 | - | - | - | - | - | Covered | T7,T8,T4 |
| StError | - | - | - | - | - | - | - | - | 2'b01 | 1 | - | - | - | - | Covered | T4,T5,T6 |
| StError | - | - | - | - | - | - | - | - | 2'b01 | 0 | - | - | - | - | Covered | T7,T8,T17 |
| StError | - | - | - | - | - | - | - | - | 2'b10 | - | - | - | - | - | Not Covered | |
| StError | - | - | - | - | - | - | - | - | 2'b11 | - | - | - | - | - | Not Covered | |
| StError | - | - | - | - | - | - | - | - | default | - | - | - | - | - | Not Covered | |
| StErrorAwaitSw | - | - | - | - | - | - | - | - | - | - | 1 | - | - | - | Covered | T7,T8,T17 |
| StErrorAwaitSw | - | - | - | - | - | - | - | - | - | - | 0 | - | - | - | Covered | T7,T8,T17 |
| StErrorAwaitApp | - | - | - | - | - | - | - | - | - | - | - | 1 | - | - | Not Covered | |
| StErrorAwaitApp | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | Not Covered | |
| StErrorWaitAbsorbed | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 1 | Not Covered | |
| StErrorWaitAbsorbed | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | Covered | T7,T8,T17 |
| StErrorWaitAbsorbed | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | Covered | T7,T8,T17 |
| StErrorServiceRejected | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T4,T5,T6 |
| StTerminalError | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T10,T11,T18 |
| default | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T18,T34,T35 |
639 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin -1- 640 st_d = StTerminalError; ==> 641 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T10,T11,T18 |
| 0 | Covered | T1,T2,T3 |
644 if (st_d != StTerminalError) begin -1- 645 // Key from keymgr is used but not valid, so abort into the invalid key error state. 646 if (keymgr_key_used && !keymgr_key_i.valid) begin -2- 647 st_d = StKeyMgrErrKeyNotValid; ==> 648 end MISSING_ELSE ==> 649 end MISSING_ELSE ==>
Branches:
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 1 | 1 | Covered | T7,T8,T17 |
| 1 | 0 | Covered | T1,T2,T3 |
| 0 | - | Covered | T10,T11,T18 |
659 if (!rst_ni) begin -1- 660 err_during_sw_q <= 1'b0; ==> 661 end else begin 662 err_during_sw_q <= err_during_sw_d; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
689 unique case (mux_sel_buf_kmac) -1- 690 SelApp: begin 691 // app_id is valid at this time 692 kmac_valid_o = app_i[app_id].valid; ==> 693 kmac_data_o = app_i[app_id].data; 694 // Expand strb to bits. prim_packer inside MSG_FIFO accepts the bit masks 695 for (int i = 0 ; i < $bits(app_i[app_id].strb) ; i++) begin 696 kmac_mask_o[8*i+:8] = {8{app_i[app_id].strb[i]}}; 697 end 698 app_data_ready = kmac_ready_i; 699 end 700 701 SelOutLen: begin 702 // Write encoded output length value 703 kmac_valid_o = 1'b 1; // always write ==> 704 kmac_data_o = MsgWidth'(encoded_outlen); 705 kmac_mask_o = MsgWidth'(encoded_outlen_mask); 706 end 707 708 SelSw: begin 709 kmac_valid_o = sw_valid_i; ==> 710 kmac_data_o = sw_data_i ; 711 kmac_mask_o = sw_mask_i ; 712 sw_ready_o = kmac_ready_i ; 713 end 714 715 default: begin // Incl. SelNone 716 kmac_valid_o = 1'b 0; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| SelApp | Covered | T10,T9,T4 |
| SelOutLen | Covered | T9,T13,T14 |
| SelSw | Covered | T1,T2,T12 |
| default | Covered | T1,T2,T3 |
728 if (mux_sel_buf_err_check != SelSw && sw_valid_i) begin -1- 729 // If SW writes message into FIFO 730 mux_err = '{ ==> 731 valid: 1'b 1, 732 code: ErrSwPushedMsgFifo, 733 info: 24'({8'h 00, 8'(st), 8'(mux_sel_buf_err_check)}) 734 }; 735 end else if (app_active_o && sw_cmd_i != CmdNone) begin -2- 736 // If SW issues command except start 737 mux_err = '{ ==> 738 valid: 1'b 1, 739 code: ErrSwIssuedCmdInAppActive, 740 info: 24'(sw_cmd_i) 741 }; 742 end MISSING_ELSE ==>
Branches:
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 1 | - | Covered | T10,T11,T18 |
| 0 | 1 | Covered | T19,T20,T21 |
| 0 | 0 | Covered | T1,T2,T3 |
792 if ((mux_sel_buf_output == SelSw) && -1- 793 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin 794 reg_state_valid = keccak_state_valid_i; 795 reg_state_o = keccak_state_i; 796 // If key is sideloaded and KMAC is SW initiated 797 // hide the capacity from SW by zeroing (see #17508) 798 if (keymgr_key_en_i) begin -2- 799 for (int i = 0; i < Share; i++) begin ==> 800 unique case (reg_keccak_strength_i) 801 L128: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L128]] = '0; 802 L224: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L224]] = '0; 803 L256: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L256]] = '0; 804 L384: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L384]] = '0; 805 L512: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L512]] = '0; 806 default: reg_state_o[i] = '0; 807 endcase 808 end 809 end MISSING_ELSE ==> 810 end MISSING_ELSE ==>
Branches:
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 1 | 1 | Covered | T22,T13,T14 |
| 1 | 0 | Covered | T1,T2,T12 |
| 0 | - | Covered | T1,T2,T3 |
817 if (st == StAppWait && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i) && -1- 818 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin 819 // SHA3 engine has calculated the hash. Return the data to KeyMgr 820 app_digest_done = 1'b 1; ==> 821 822 // digest has always 2 entries. If !EnMasking, second is tied to 0. 823 for (int i = 0 ; i < Share ; i++) begin 824 // Return the portion of state. 825 app_digest[i] = keccak_state_i[i][AppDigestW-1:0]; 826 end 827 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T9,T4,T5 |
| 0 | Covered | T1,T2,T3 |
862 unique case (st) -1- 863 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin 864 // Key from keymgr is actually used if the current HW app interface does *keyed* MAC. 865 keymgr_key_used = AppCfg[app_id].Mode == AppKMAC; ==> 866 key_len_o = SideloadedKey; 867 for (int i = 0 ; i < Share; i++) begin 868 key_data_o[i] = keymgr_key[i]; 869 end 870 // Key is valid if the current HW app interface does *keyed* MAC and the key provided by 871 // keymgr is valid. 872 key_valid_o = keymgr_key_used && keymgr_key_i.valid; 873 end 874 875 StSw: begin 876 if (keymgr_key_en_i) begin -2- 877 // Key from keymgr is actually used if *keyed* MAC is enabled. 878 keymgr_key_used = kmac_en_o; ==> 879 key_len_o = SideloadedKey; 880 for (int i = 0 ; i < Share; i++) begin 881 key_data_o[i] = keymgr_key[i]; 882 end 883 end MISSING_ELSE ==> 884 // Key is valid if SW does *keyed* MAC and ... 885 if (kmac_en_o) begin -3- 886 if (!keymgr_key_en_i) begin -4- 887 // ... it uses the key from kmac's CSR, or ... 888 key_valid_o = 1'b1; ==> 889 end else begin 890 // ... it uses the key provided by keymgr and that one is valid. 891 key_valid_o = keymgr_key_i.valid; ==> 892 end 893 end MISSING_ELSE ==> 894 end 895 896 default: ; ==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
|---|---|---|---|---|---|
| StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait | - | - | - | Covered | T7,T10,T8 |
| StSw | 1 | - | - | Covered | T22,T13,T14 |
| StSw | 0 | - | - | Covered | T1,T2,T12 |
| StSw | - | 1 | 1 | Covered | T1,T2,T12 |
| StSw | - | 1 | 0 | Covered | T13,T14,T15 |
| StSw | - | 0 | - | Covered | T22,T27,T38 |
| default | - | - | - | Covered | T1,T2,T3 |
906 unique case (st) -1- 907 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin 908 // Check app intf cfg 909 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin ==> 910 if (app_id == i) begin 911 if (AppCfg[i].PrefixMode == 1'b 0) begin 912 sha3_prefix_o = reg_prefix_i; 913 end else begin 914 sha3_prefix_o = AppCfg[i].Prefix; 915 end 916 end 917 end 918 end 919 920 StSw: begin 921 sha3_prefix_o = reg_prefix_i; ==> 922 end 923 924 default: begin 925 sha3_prefix_o = reg_prefix_i; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait | Covered | T7,T10,T8 |
| StSw | Covered | T1,T2,T12 |
| default | Covered | T1,T2,T3 |
933 if (!rst_ni) begin -1- 934 kmac_en_o <= 1'b 0; ==> 935 sha3_mode_o <= sha3_pkg::Sha3; 936 keccak_strength_o <= sha3_pkg::L256; 937 end else if (clr_appid) begin -2- 938 // As App completed, latch reg value 939 kmac_en_o <= reg_kmac_en_i; ==> 940 sha3_mode_o <= reg_sha3_mode_i; 941 keccak_strength_o <= reg_keccak_strength_i; 942 end else if (set_appid) begin -3- 943 kmac_en_o <= AppCfg[arb_idx].Mode == AppKMAC ? 1'b 1 : 1'b 0; -4- ==> ==> 944 sha3_mode_o <= AppCfg[arb_idx].Mode == AppSHA3 945 ? sha3_pkg::Sha3 : sha3_pkg::CShake; -5- ==> ==> 946 keccak_strength_o <= AppCfg[arb_idx].Strength ; 947 end else if (st == StIdle) begin -6- 948 kmac_en_o <= reg_kmac_en_i; ==> 949 sha3_mode_o <= reg_sha3_mode_i; 950 keccak_strength_o <= reg_keccak_strength_i; 951 end MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
|---|---|---|---|---|---|---|---|
| 1 | - | - | - | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | - | - | - | Covered | T7,T8,T9 |
| 0 | 0 | 1 | 1 | - | - | Covered | T7,T10,T8 |
| 0 | 0 | 1 | 0 | - | - | Covered | T9,T4,T5 |
| 0 | 0 | 1 | - | 1 | - | Not Covered | |
| 0 | 0 | 1 | - | 0 | - | Covered | T7,T10,T8 |
| 0 | 0 | 0 | - | - | 1 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | - | - | 0 | Covered | T1,T2,T7 |
960 priority casez ({fsm_err.valid, mux_err.valid}) -1- 961 2'b ?1: error_o = mux_err; ==> 962 2'b 10: error_o = fsm_err; ==> 963 default: error_o = '{valid: 1'b0, code: ErrNone, info: '0}; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 2'bz1 | Covered | T10,T11,T18 |
| 2'b10 | Covered | T7,T10,T8 |
| default | Covered | T1,T2,T3 |
Assert Coverage for Module : kmac_app
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
| Cover properties | 1 | 1 | 100.00 | 1 | 100.00 |
| Cover sequences | 0 | 0 | 0 | ||
| Total | 4 | 4 | 100.00 | 4 | 100.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| AppIntfInRange_A | 669 | 669 | 0 | 0 |
| SideloadKeySameToDigest_A | 669 | 669 | 0 | 0 |
| u_state_regs_A | 621131667 | 620970968 | 0 | 0 |
AppIntfInRange_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 669 | 669 | 0 | 0 |
| T1 | 1 | 1 | 0 | 0 |
| T2 | 1 | 1 | 0 | 0 |
| T3 | 1 | 1 | 0 | 0 |
| T7 | 1 | 1 | 0 | 0 |
| T10 | 1 | 1 | 0 | 0 |
| T12 | 1 | 1 | 0 | 0 |
| T22 | 1 | 1 | 0 | 0 |
| T27 | 1 | 1 | 0 | 0 |
| T38 | 1 | 1 | 0 | 0 |
| T39 | 1 | 1 | 0 | 0 |
SideloadKeySameToDigest_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 669 | 669 | 0 | 0 |
| T1 | 1 | 1 | 0 | 0 |
| T2 | 1 | 1 | 0 | 0 |
| T3 | 1 | 1 | 0 | 0 |
| T7 | 1 | 1 | 0 | 0 |
| T10 | 1 | 1 | 0 | 0 |
| T12 | 1 | 1 | 0 | 0 |
| T22 | 1 | 1 | 0 | 0 |
| T27 | 1 | 1 | 0 | 0 |
| T38 | 1 | 1 | 0 | 0 |
| T39 | 1 | 1 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 621131667 | 620970968 | 0 | 0 |
| T1 | 3295 | 3229 | 0 | 0 |
| T2 | 2952 | 2858 | 0 | 0 |
| T3 | 781 | 693 | 0 | 0 |
| T7 | 6479 | 6394 | 0 | 0 |
| T10 | 4028 | 3883 | 0 | 0 |
| T12 | 9510 | 9458 | 0 | 0 |
| T22 | 51743 | 51689 | 0 | 0 |
| T27 | 40396 | 40325 | 0 | 0 |
| T38 | 107016 | 106926 | 0 | 0 |
| T39 | 5633 | 5565 | 0 | 0 |
Cover Directives for Properties: Details
| Name | Attempts | Matches | Incomplete |
| AppIntfUseDifferentSizeKey_C | 621131667 | 2611 | 0 |
AppIntfUseDifferentSizeKey_C
| Name | Attempts | Matches | Incomplete |
|---|---|---|---|
| Total | 621131667 | 2611 | 0 |
| T5 | 0 | 34 | 0 |
| T6 | 0 | 47 | 0 |
| T7 | 6479 | 1 | 0 |
| T8 | 20698 | 1 | 0 |
| T9 | 0 | 3 | 0 |
| T10 | 4028 | 1 | 0 |
| T12 | 9510 | 0 | 0 |
| T13 | 0 | 14 | 0 |
| T14 | 0 | 2 | 0 |
| T15 | 0 | 25 | 0 |
| T17 | 0 | 7 | 0 |
| T22 | 51743 | 0 | 0 |
| T27 | 40396 | 0 | 0 |
| T38 | 107016 | 0 | 0 |
| T39 | 5633 | 0 | 0 |
| T40 | 81775 | 0 | 0 |
| T41 | 3378 | 0 | 0 |