Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622478545	63335613	0	0
DataKnown_AKnownEnable	622478545	622265977	0	0
DepthKnown_A	622478545	622265977	0	0
RvalidKnown_A	622478545	622265977	0	0
WreadyKnown_A	622478545	622265977	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	63335613	0	0
T1	3295	416	0	0
T2	2952	600	0	0
T3	781	17	0	0
T7	6479	78	0	0
T10	4028	86	0	0
T12	9510	628	0	0
T22	51743	3919	0	0
T27	40396	2227	0	0
T38	107016	4109	0	0
T39	5633	598	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622478545	110138930	0	0
DataKnown_AKnownEnable	622478545	622265977	0	0
DepthKnown_A	622478545	622265977	0	0
RvalidKnown_A	622478545	622265977	0	0
WreadyKnown_A	622478545	622265977	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	110138930	0	0
T1	3295	416	0	0
T2	2952	600	0	0
T3	781	17	0	0
T7	6479	340	0	0
T10	4028	364	0	0
T12	9510	628	0	0
T22	51743	3919	0	0
T27	40396	6580	0	0
T38	107016	12716	0	0
T39	5633	598	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	622265977	0	0
T1	3295	3229	0	0
T2	2952	2858	0	0
T3	781	693	0	0
T7	6479	6394	0	0
T10	4028	3883	0	0
T12	9510	9458	0	0
T22	51743	51689	0	0
T27	40396	40325	0	0
T38	107016	106926	0	0
T39	5633	5565	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T27	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0