Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	622478545	15623	0	0
entropy_period_rd_A	622478545	1853	0	0
intr_enable_rd_A	622478545	2628	0	0
prefix_0_rd_A	622478545	1912	0	0
prefix_10_rd_A	622478545	1908	0	0
prefix_1_rd_A	622478545	1834	0	0
prefix_2_rd_A	622478545	1835	0	0
prefix_3_rd_A	622478545	1921	0	0
prefix_4_rd_A	622478545	1889	0	0
prefix_5_rd_A	622478545	1927	0	0
prefix_6_rd_A	622478545	1886	0	0
prefix_7_rd_A	622478545	2028	0	0
prefix_8_rd_A	622478545	1752	0	0
prefix_9_rd_A	622478545	1840	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	15623	0	0
T14	365806	4930	0	0
T15	643734	0	0	0
T16	709175	0	0	0
T23	833179	0	0	0
T26	973168	0	0	0
T35	265369	0	0	0
T51	0	2166	0	0
T52	0	1271	0	0
T68	275652	0	0	0
T69	844280	0	0	0
T70	479732	0	0	0
T71	7232	0	0	0
T125	0	1	0	0
T131	0	3715	0	0
T132	0	200	0	0
T133	0	187	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	254	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1853	0	0
T52	152851	22	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	62	0	0
T106	0	11	0	0
T110	0	12	0	0
T126	0	27	0	0
T129	0	5	0	0
T134	0	10	0	0
T149	0	10	0	0
T150	0	3	0	0
T151	0	27	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	2628	0	0
T52	152851	23	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	92	0	0
T105	0	10	0	0
T106	0	12	0	0
T110	0	19	0	0
T126	0	41	0	0
T128	0	29	0	0
T134	0	1	0	0
T149	0	23	0	0
T150	0	6	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1912	0	0
T52	152851	27	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	65	0	0
T106	0	11	0	0
T108	0	8	0	0
T110	0	24	0	0
T126	0	22	0	0
T134	0	5	0	0
T149	0	8	0	0
T150	0	4	0	0
T151	0	11	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1908	0	0
T52	152851	24	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	62	0	0
T105	0	8	0	0
T106	0	12	0	0
T110	0	22	0	0
T126	0	37	0	0
T129	0	6	0	0
T134	0	9	0	0
T149	0	14	0	0
T150	0	1	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1834	0	0
T52	152851	13	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	43	0	0
T105	0	10	0	0
T106	0	11	0	0
T110	0	13	0	0
T126	0	32	0	0
T134	0	15	0	0
T149	0	2	0	0
T151	0	26	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0
T159	0	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1835	0	0
T52	152851	35	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	51	0	0
T105	0	1	0	0
T106	0	8	0	0
T110	0	14	0	0
T126	0	25	0	0
T134	0	9	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	17	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1921	0	0
T52	152851	18	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	67	0	0
T105	0	7	0	0
T106	0	4	0	0
T110	0	24	0	0
T126	0	14	0	0
T129	0	4	0	0
T134	0	10	0	0
T149	0	2	0	0
T150	0	8	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1889	0	0
T52	152851	31	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	64	0	0
T106	0	11	0	0
T110	0	15	0	0
T126	0	27	0	0
T129	0	4	0	0
T134	0	4	0	0
T149	0	9	0	0
T150	0	2	0	0
T151	0	20	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1927	0	0
T52	152851	15	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	62	0	0
T105	0	5	0	0
T106	0	11	0	0
T110	0	24	0	0
T126	0	22	0	0
T129	0	2	0	0
T134	0	10	0	0
T149	0	4	0	0
T150	0	2	0	0
T152	165354	0	0	0
T153	204896	0	0	0
T154	357357	0	0	0
T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1886	0	0
T52	152851	23	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	53	0	0
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T106	0	13	0	0
T110	0	22	0	0
T126	0	30	0	0
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T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	2028	0	0
T52	152851	19	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	65	0	0
T105	0	2	0	0
T106	0	7	0	0
T110	0	16	0	0
T126	0	33	0	0
T129	0	3	0	0
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T150	0	9	0	0
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T153	204896	0	0	0
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T155	267885	0	0	0
T156	430169	0	0	0
T157	44619	0	0	0
T158	1764	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1752	0	0
T52	152851	30	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	58	0	0
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T157	44619	0	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622478545	1840	0	0
T52	152851	20	0	0
T65	189903	0	0	0
T66	316172	0	0	0
T104	0	62	0	0
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