| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.14 | 97.90 | 92.65 | 99.89 | 76.06 | 95.57 | 99.07 | 97.88 |
| T760 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2500297635 | Oct 02 11:18:25 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 58184472 ps | ||
| T761 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2006203696 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 16947260 ps | ||
| T762 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1056898245 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 65221517 ps | ||
| T763 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3803553809 | Oct 02 11:18:25 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 163409549 ps | ||
| T764 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4088029142 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 28146939 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.696835534 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 19373145 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.3364599474 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 17927592 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.408239875 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:32 PM UTC 24 | 63402372 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1299118130 | Oct 02 11:18:28 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 274822073 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1687499722 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 94333207 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1225245344 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 84725859 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.838190359 | Oct 02 11:18:20 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 45873216 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4056435335 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 165248132 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3371033512 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 332918714 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.826647168 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 33410189 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1481395242 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 50859450 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.4151338799 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 30356380 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2584035990 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 41136380 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1584417376 | Oct 02 11:18:21 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 131490265 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3738298457 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 40563295 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1100690562 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 173748992 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3346204760 | Oct 02 11:18:28 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 159515708 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.555214909 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 408556411 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4129870287 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 69207282 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.638427804 | Oct 02 11:18:21 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 277864503 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.673224209 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 171467098 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2899906577 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 79962543 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3480663416 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:33 PM UTC 24 | 526194171 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3667248435 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:34 PM UTC 24 | 87262631 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.231637597 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:34 PM UTC 24 | 291568185 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1133708530 | Oct 02 11:18:22 PM UTC 24 | Oct 02 11:18:34 PM UTC 24 | 173712044 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1467612189 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:34 PM UTC 24 | 20673029 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1486852170 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:34 PM UTC 24 | 145060196 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1224085875 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:34 PM UTC 24 | 43787822 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3383116878 | Oct 02 11:18:28 PM UTC 24 | Oct 02 11:18:34 PM UTC 24 | 185328426 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2931619402 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:35 PM UTC 24 | 46754224 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1021558336 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:35 PM UTC 24 | 149587961 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1112554847 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:35 PM UTC 24 | 202513884 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1332742604 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:35 PM UTC 24 | 40425260 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3758065815 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:35 PM UTC 24 | 127855681 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3546125504 | Oct 02 11:18:23 PM UTC 24 | Oct 02 11:18:35 PM UTC 24 | 383543197 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3243713179 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:35 PM UTC 24 | 110657794 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.362761923 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:36 PM UTC 24 | 207062128 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.238507403 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:36 PM UTC 24 | 488344047 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3906136367 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:36 PM UTC 24 | 28748331 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2003097565 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:36 PM UTC 24 | 36376390 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.581639566 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:36 PM UTC 24 | 91402752 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2131902024 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:37 PM UTC 24 | 26403783 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1578872340 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:37 PM UTC 24 | 151068512 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.182218841 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:37 PM UTC 24 | 56695975 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3371210609 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:37 PM UTC 24 | 65734367 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.819284762 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:37 PM UTC 24 | 69555399 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.637743101 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:37 PM UTC 24 | 74817628 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.523414694 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:38 PM UTC 24 | 188356691 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1518962160 | Oct 02 11:18:32 PM UTC 24 | Oct 02 11:18:38 PM UTC 24 | 241268013 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1474952957 | Oct 02 11:18:34 PM UTC 24 | Oct 02 11:18:38 PM UTC 24 | 492519987 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3633856261 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:39 PM UTC 24 | 552440413 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3309222334 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 16942893 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.788052872 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 278189948 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1971101902 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 90587769 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.615403650 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 72768125 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1555769966 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 23681701 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2047846591 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 23926618 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2579490259 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 13821416 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1181898409 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:40 PM UTC 24 | 21419180 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2907838304 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 48678338 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1559732051 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 348902819 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2271765030 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 417314000 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2949696105 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 167445553 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.900280940 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 102044528 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.850918208 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 216440635 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.945609284 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 152761904 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1541146017 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 55245854 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.92470349 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 18750510 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3616272404 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 107550353 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3607934872 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 24016491 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1857225565 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 136891723 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1880716674 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 27319517 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.365313295 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 24993382 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3814453984 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 27844394 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2938209861 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 21934847 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1362289780 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 11872723 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.458278901 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 15143288 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.956049044 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 102759390 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1113713013 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 188590766 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2407664252 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 86296362 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2837972520 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 83501426 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.4099661294 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 311131997 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2109109466 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 25865214 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2934900171 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:41 PM UTC 24 | 178593072 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.474525587 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 55453724 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2819606938 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 356024145 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2781653739 | Oct 02 11:18:36 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 115259123 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2299679765 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 99774178 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2538005676 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 115213731 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2123005964 | Oct 02 11:18:16 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 9026076360 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2779018160 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 161298813 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.714889021 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 198662195 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1878726872 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:42 PM UTC 24 | 459491764 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.470008283 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:43 PM UTC 24 | 488271960 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4095296419 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:18:43 PM UTC 24 | 287775497 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3335521482 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:44 PM UTC 24 | 510142486 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3304509061 | Oct 02 11:18:38 PM UTC 24 | Oct 02 11:18:44 PM UTC 24 | 722543722 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2551797101 | Oct 02 11:18:17 PM UTC 24 | Oct 02 11:18:45 PM UTC 24 | 297424142 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3274275847 | Oct 02 11:18:40 PM UTC 24 | Oct 02 11:18:55 PM UTC 24 | 18504672 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2632439566 | Oct 02 11:18:40 PM UTC 24 | Oct 02 11:18:55 PM UTC 24 | 14240551 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2032444253 | Oct 02 11:18:40 PM UTC 24 | Oct 02 11:18:55 PM UTC 24 | 137889388 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.709847966 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:02 PM UTC 24 | 13277494 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.75206173 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:02 PM UTC 24 | 17889325 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2851551896 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:02 PM UTC 24 | 20547421 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.595963117 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:02 PM UTC 24 | 44594438 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.334689859 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:02 PM UTC 24 | 24722997 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1811425522 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:02 PM UTC 24 | 15833281 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3690551287 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:02 PM UTC 24 | 21869690 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2972491943 | Oct 02 11:18:40 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 24620048 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3729335399 | Oct 02 11:18:40 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 20021584 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2954088690 | Oct 02 11:18:40 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 35297044 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2617205647 | Oct 02 11:18:41 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 38789157 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1734205989 | Oct 02 11:18:41 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 13458787 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.659055276 | Oct 02 11:18:40 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 18587426 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3249810870 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 46486607 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2491788283 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 19327354 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2027428928 | Oct 02 11:18:35 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 987686248 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1250551753 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 49562698 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2706690267 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 18767595 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1055599124 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 21506710 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2532961843 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 52591259 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3477923072 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 134689608 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1123539376 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 30555752 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.587001840 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 13771822 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.496898789 | Oct 02 11:18:43 PM UTC 24 | Oct 02 11:19:03 PM UTC 24 | 12966895 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3904413497 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 225364116 ps |
| CPU time | 4.56 seconds |
| Started | Oct 03 02:04:01 AM UTC 24 |
| Finished | Oct 03 02:04:06 AM UTC 24 |
| Peak memory | 236448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904413497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3904413497 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.332152886 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10107009057 ps |
| CPU time | 186.09 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:06:57 AM UTC 24 |
| Peak memory | 355340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332152886 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.332152886 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2919692933 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 151842178 ps |
| CPU time | 2.6 seconds |
| Started | Oct 02 11:17:59 PM UTC 24 |
| Finished | Oct 02 11:18:03 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919692933 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.2919 692933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.3862092973 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13546378715 ps |
| CPU time | 117.36 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:05:49 AM UTC 24 |
| Peak memory | 305292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862092973 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3862092973 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.1968023311 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7316160070 ps |
| CPU time | 198.66 seconds |
| Started | Oct 03 02:04:14 AM UTC 24 |
| Finished | Oct 03 02:07:36 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1968023311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_r and_reset.1968023311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.2105549096 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4280692454 ps |
| CPU time | 21.45 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:04:10 AM UTC 24 |
| Peak memory | 236840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105549096 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2105549096 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.1585371996 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 103392343 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 02:24:49 AM UTC 24 |
| Finished | Oct 03 02:24:52 AM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585371996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1585371996 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.2840806628 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 213399183 ps |
| CPU time | 3.8 seconds |
| Started | Oct 03 02:04:07 AM UTC 24 |
| Finished | Oct 03 02:04:12 AM UTC 24 |
| Peak memory | 228312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840806628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2840806628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_error.112526781 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11713399398 ps |
| CPU time | 276.18 seconds |
| Started | Oct 03 02:11:27 AM UTC 24 |
| Finished | Oct 03 02:16:08 AM UTC 24 |
| Peak memory | 457764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112526781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.112526781 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.4289960110 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 89717796 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 02:16:20 AM UTC 24 |
| Finished | Oct 03 02:16:23 AM UTC 24 |
| Peak memory | 232540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289960110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.4289960110 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3067504002 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 23189549 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:17 PM UTC 24 |
| Peak memory | 224572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067504002 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3067504002 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.130772104 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 75071014537 ps |
| CPU time | 63.77 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:04:55 AM UTC 24 |
| Peak memory | 236760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130772104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.130772104 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.1309061944 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 67596045 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 02:04:10 AM UTC 24 |
| Finished | Oct 03 02:04:12 AM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309061944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1309061944 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3383116878 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 185328426 ps |
| CPU time | 4.18 seconds |
| Started | Oct 02 11:18:28 PM UTC 24 |
| Finished | Oct 02 11:18:34 PM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383116878 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3383116878 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.1775154382 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 92803282 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 02:43:40 AM UTC 24 |
| Finished | Oct 03 02:43:43 AM UTC 24 |
| Peak memory | 232532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775154382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1775154382 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.3523263047 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 745154063 ps |
| CPU time | 22.94 seconds |
| Started | Oct 03 03:04:00 AM UTC 24 |
| Finished | Oct 03 03:04:24 AM UTC 24 |
| Peak memory | 248872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523263047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3523263047 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.3328539833 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 159725753 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 02:04:11 AM UTC 24 |
| Finished | Oct 03 02:04:13 AM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328539833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3328539833 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.523697083 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 38755486943 ps |
| CPU time | 875.31 seconds |
| Started | Oct 03 02:04:14 AM UTC 24 |
| Finished | Oct 03 02:19:00 AM UTC 24 |
| Peak memory | 466300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523697083 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.523697083 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.922776883 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 14495746403 ps |
| CPU time | 333.97 seconds |
| Started | Oct 03 02:11:15 AM UTC 24 |
| Finished | Oct 03 02:16:54 AM UTC 24 |
| Peak memory | 341012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922776883 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.922776883 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.3511358884 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 31492492 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 11:17:53 PM UTC 24 |
| Finished | Oct 02 11:17:56 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511358884 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.3511358884 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.2367393794 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 201456610 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:03:52 AM UTC 24 |
| Peak memory | 232540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367393794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2367393794 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.2834821431 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 103767159 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 02:36:28 AM UTC 24 |
| Finished | Oct 03 02:36:31 AM UTC 24 |
| Peak memory | 232092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834821431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2834821431 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.2843409057 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 51367426 ps |
| CPU time | 2.05 seconds |
| Started | Oct 03 02:12:09 AM UTC 24 |
| Finished | Oct 03 02:12:12 AM UTC 24 |
| Peak memory | 230636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843409057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2843409057 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.1814334729 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 31343904 ps |
| CPU time | 0.95 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:03:51 AM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814334729 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1814334729 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.996568228 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 10672777099 ps |
| CPU time | 149.97 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:06:20 AM UTC 24 |
| Peak memory | 267292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996568228 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.996568228 +ena ble_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.288137023 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 25189060 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288137023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.288137023 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.3386785092 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 16744632452 ps |
| CPU time | 89.13 seconds |
| Started | Oct 03 02:04:18 AM UTC 24 |
| Finished | Oct 03 02:05:49 AM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386785092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3386785092 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.523414694 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 188356691 ps |
| CPU time | 2.5 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:38 PM UTC 24 |
| Peak memory | 226272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523414694 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.523414694 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.1387120580 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 5430104284 ps |
| CPU time | 10.31 seconds |
| Started | Oct 03 02:57:02 AM UTC 24 |
| Finished | Oct 03 02:57:13 AM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387120580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1387120580 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3309222334 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 16942893 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309222334 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3309222334 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.2900991521 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 105499188 ps |
| CPU time | 2.62 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:24 PM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900991521 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.2900991521 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.1829056453 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 8890623505 ps |
| CPU time | 355.65 seconds |
| Started | Oct 03 02:53:47 AM UTC 24 |
| Finished | Oct 03 02:59:48 AM UTC 24 |
| Peak memory | 419032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829056453 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1829056453 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.3889447855 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 159250298052 ps |
| CPU time | 1745.17 seconds |
| Started | Oct 03 02:09:54 AM UTC 24 |
| Finished | Oct 03 02:39:19 AM UTC 24 |
| Peak memory | 364200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889447855 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3889447855 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2301110387 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 293584980 ps |
| CPU time | 4.16 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:08 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301110387 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2301110387 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_error.3286400360 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4747388987 ps |
| CPU time | 337.02 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:09:31 AM UTC 24 |
| Peak memory | 369708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286400360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3286400360 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.1895813712 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 33911226208 ps |
| CPU time | 42.31 seconds |
| Started | Oct 03 02:06:46 AM UTC 24 |
| Finished | Oct 03 02:07:30 AM UTC 24 |
| Peak memory | 236560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895813712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1895813712 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.2327156241 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6114112553 ps |
| CPU time | 63.31 seconds |
| Started | Oct 03 02:16:41 AM UTC 24 |
| Finished | Oct 03 02:17:47 AM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2327156241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_r and_reset.2327156241 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.2516737044 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11413752930 ps |
| CPU time | 248.2 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:08:01 AM UTC 24 |
| Peak memory | 448092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516737044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2516737044 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2990080783 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 291864674 ps |
| CPU time | 7.24 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:11 PM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990080783 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2990080783 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1342340111 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 64292665 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:05 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342340111 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1342340111 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3872288230 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 162891477 ps |
| CPU time | 1.46 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:06 PM UTC 24 |
| Peak memory | 228596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3872288230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_ rw_with_rand_reset.3872288230 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2158897974 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 119977803 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:05 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158897974 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2158897974 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.3585171716 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 26413500 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:05 PM UTC 24 |
| Peak memory | 224276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585171716 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3585171716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.3916365264 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 21069392 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 11:17:53 PM UTC 24 |
| Finished | Oct 02 11:17:55 PM UTC 24 |
| Peak memory | 224940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916365264 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3916365264 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3680851198 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 54335081 ps |
| CPU time | 1.59 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:06 PM UTC 24 |
| Peak memory | 224464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680851198 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.3680851198 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.4191712355 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 119599040 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 11:17:53 PM UTC 24 |
| Finished | Oct 02 11:18:06 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191712355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.4191712355 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3964661827 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 85692491 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 11:17:53 PM UTC 24 |
| Finished | Oct 02 11:18:07 PM UTC 24 |
| Peak memory | 228592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964661827 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.3964 661827 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.1019529268 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 101666646 ps |
| CPU time | 2.36 seconds |
| Started | Oct 02 11:17:53 PM UTC 24 |
| Finished | Oct 02 11:17:57 PM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019529268 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1019529268 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.418750392 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 97354209 ps |
| CPU time | 2.43 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:06 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418750392 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.418750392 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.3580604556 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 208189945 ps |
| CPU time | 4.31 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580604556 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3580604556 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.3459414355 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1240967701 ps |
| CPU time | 9.51 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:26 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459414355 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3459414355 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.3212272097 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 92826369 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:18 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212272097 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3212272097 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4093356738 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 153586909 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:18 PM UTC 24 |
| Peak memory | 228596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4093356738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_ rw_with_rand_reset.4093356738 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.788726272 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 86401879 ps |
| CPU time | 1.07 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:18 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788726272 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.788726272 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.4007607305 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 24155670 ps |
| CPU time | 1.22 seconds |
| Started | Oct 02 11:17:59 PM UTC 24 |
| Finished | Oct 02 11:18:02 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007607305 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.4007607305 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.89792274 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 32781179 ps |
| CPU time | 0.69 seconds |
| Started | Oct 02 11:17:59 PM UTC 24 |
| Finished | Oct 02 11:18:01 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89792274 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.89792274 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.740174801 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 39204181 ps |
| CPU time | 1.99 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:19 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740174801 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.740174801 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.57418107 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 241863706 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 11:17:57 PM UTC 24 |
| Finished | Oct 02 11:18:05 PM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57418107 -assert nopostproc + UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.57418107 +enable_masking=1 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.901455755 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 289683529 ps |
| CPU time | 2.02 seconds |
| Started | Oct 02 11:17:59 PM UTC 24 |
| Finished | Oct 02 11:18:02 PM UTC 24 |
| Peak memory | 226060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901455755 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.901455755 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1877149500 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 341236289 ps |
| CPU time | 3.82 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877149500 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.1877149500 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.981801158 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 771318378 ps |
| CPU time | 1.56 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:31 PM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=981801158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_ rw_with_rand_reset.981801158 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.4223940283 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 181322977 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:30 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223940283 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.4223940283 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2845923973 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 38841246 ps |
| CPU time | 0.74 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:30 PM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845923973 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2845923973 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3426533286 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 380920603 ps |
| CPU time | 1.61 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:31 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426533286 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.3426533286 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.408239875 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 63402372 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408239875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.408239875 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2664137701 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 41575429 ps |
| CPU time | 1.58 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:31 PM UTC 24 |
| Peak memory | 230712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664137701 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.266 4137701 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3803553809 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 163409549 ps |
| CPU time | 2.69 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803553809 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3803553809 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2500297635 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 58184472 ps |
| CPU time | 2.24 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 225936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500297635 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2500297635 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1332742604 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 40425260 ps |
| CPU time | 2.31 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:35 PM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1332742604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem _rw_with_rand_reset.1332742604 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1336357108 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 50069479 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 11:18:30 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336357108 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1336357108 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.26012409 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 37125511 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 11:18:30 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26012409 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.26012409 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3243713179 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 110657794 ps |
| CPU time | 2.32 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:35 PM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243713179 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3243713179 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3710806357 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 70987337 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 11:18:25 PM UTC 24 |
| Finished | Oct 02 11:18:31 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710806357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.3710806357 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1299118130 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 274822073 ps |
| CPU time | 2.71 seconds |
| Started | Oct 02 11:18:28 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299118130 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.129 9118130 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3346204760 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 159515708 ps |
| CPU time | 3.29 seconds |
| Started | Oct 02 11:18:28 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346204760 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3346204760 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.819284762 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 69555399 ps |
| CPU time | 2.02 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:37 PM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=819284762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_ rw_with_rand_reset.819284762 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2931619402 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 46754224 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:35 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931619402 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2931619402 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1467612189 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 20673029 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:34 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467612189 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1467612189 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3758065815 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 127855681 ps |
| CPU time | 1.89 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:35 PM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758065815 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.3758065815 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1224085875 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 43787822 ps |
| CPU time | 1.16 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:34 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224085875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.1224085875 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.238507403 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 488344047 ps |
| CPU time | 2.96 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:36 PM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238507403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.2385 07403 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.362761923 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 207062128 ps |
| CPU time | 2.83 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:36 PM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362761923 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.362761923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1518962160 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 241268013 ps |
| CPU time | 4.76 seconds |
| Started | Oct 02 11:18:32 PM UTC 24 |
| Finished | Oct 02 11:18:38 PM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518962160 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1518962160 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3371210609 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 65734367 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:37 PM UTC 24 |
| Peak memory | 226388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3371210609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem _rw_with_rand_reset.3371210609 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2003097565 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 36376390 ps |
| CPU time | 0.87 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:36 PM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003097565 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2003097565 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3906136367 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 28748331 ps |
| CPU time | 0.74 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:36 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906136367 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3906136367 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.182218841 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 56695975 ps |
| CPU time | 1.43 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:37 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182218841 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.182218841 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.581639566 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 91402752 ps |
| CPU time | 1.34 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:36 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581639566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.581639566 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1578872340 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 151068512 ps |
| CPU time | 1.58 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:37 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578872340 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.157 8872340 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.637743101 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 74817628 ps |
| CPU time | 2.1 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:37 PM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637743101 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.637743101 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1857225565 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 136891723 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 232336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1857225565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem _rw_with_rand_reset.1857225565 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2131902024 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 26403783 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:37 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131902024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.2131902024 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1474952957 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 492519987 ps |
| CPU time | 2.63 seconds |
| Started | Oct 02 11:18:34 PM UTC 24 |
| Finished | Oct 02 11:18:38 PM UTC 24 |
| Peak memory | 225952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474952957 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.147 4952957 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3633856261 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 552440413 ps |
| CPU time | 3.15 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:39 PM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633856261 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3633856261 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.788052872 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 278189948 ps |
| CPU time | 4.08 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 226128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788052872 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.788052872 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.945609284 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 152761904 ps |
| CPU time | 1.57 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=945609284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_ rw_with_rand_reset.945609284 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.615403650 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 72768125 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615403650 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.615403650 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2271765030 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 417314000 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271765030 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.2271765030 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1971101902 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 90587769 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971101902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.1971101902 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1113713013 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 188590766 ps |
| CPU time | 2.25 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113713013 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.111 3713013 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1559732051 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 348902819 ps |
| CPU time | 2.29 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559732051 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1559732051 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4095296419 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 287775497 ps |
| CPU time | 4.12 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:43 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095296419 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.4095296419 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.4099661294 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 311131997 ps |
| CPU time | 2.11 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4099661294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem _rw_with_rand_reset.4099661294 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1181898409 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 21419180 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181898409 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1181898409 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2047846591 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 23926618 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047846591 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2047846591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2819606938 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 356024145 ps |
| CPU time | 2.31 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819606938 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.2819606938 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1555769966 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 23681701 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555769966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.1555769966 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2407664252 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 86296362 ps |
| CPU time | 2.15 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407664252 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.240 7664252 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1878726872 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 459491764 ps |
| CPU time | 3.1 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878726872 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1878726872 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2027428928 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 987686248 ps |
| CPU time | 3.74 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 226200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027428928 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2027428928 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2781653739 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 115259123 ps |
| CPU time | 2.14 seconds |
| Started | Oct 02 11:18:36 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2781653739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem _rw_with_rand_reset.2781653739 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.900280940 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 102044528 ps |
| CPU time | 1.16 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900280940 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.900280940 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2579490259 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 13821416 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:40 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579490259 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2579490259 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1880716674 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 27319517 ps |
| CPU time | 1.39 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880716674 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.1880716674 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2949696105 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 167445553 ps |
| CPU time | 1.31 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949696105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2949696105 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.474525587 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 55453724 ps |
| CPU time | 2.12 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474525587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.4745 25587 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.956049044 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 102759390 ps |
| CPU time | 1.74 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956049044 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.956049044 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2779018160 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 161298813 ps |
| CPU time | 2.7 seconds |
| Started | Oct 02 11:18:35 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779018160 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2779018160 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2538005676 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 115213731 ps |
| CPU time | 2.13 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2538005676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem _rw_with_rand_reset.2538005676 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3616272404 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 107550353 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616272404 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3616272404 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2907838304 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 48678338 ps |
| CPU time | 0.81 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907838304 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2907838304 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2837972520 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 83501426 ps |
| CPU time | 1.58 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837972520 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.2837972520 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1541146017 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 55245854 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541146017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.1541146017 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.714889021 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 198662195 ps |
| CPU time | 2.68 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714889021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.7148 89021 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.850918208 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 216440635 ps |
| CPU time | 1.82 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850918208 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.850918208 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3335521482 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 510142486 ps |
| CPU time | 4.29 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:44 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335521482 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3335521482 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2299679765 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 99774178 ps |
| CPU time | 1.72 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2299679765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem _rw_with_rand_reset.2299679765 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2938209861 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 21934847 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938209861 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2938209861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.92470349 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 18750510 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92470349 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.92470349 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2109109466 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 25865214 ps |
| CPU time | 1.37 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109109466 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.2109109466 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3814453984 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 27844394 ps |
| CPU time | 1.07 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814453984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.3814453984 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2934900171 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 178593072 ps |
| CPU time | 1.53 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934900171 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.293 4900171 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.470008283 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 488271960 ps |
| CPU time | 3.13 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:43 PM UTC 24 |
| Peak memory | 225992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470008283 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.470008283 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3304509061 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 722543722 ps |
| CPU time | 4.27 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:44 PM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304509061 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3304509061 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.2722507403 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 981921464 ps |
| CPU time | 5.14 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:25 PM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722507403 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2722507403 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2123005964 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 9026076360 ps |
| CPU time | 21.61 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:42 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123005964 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2123005964 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1558859632 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 291216118 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558859632 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1558859632 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2745853818 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 142206209 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:23 PM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2745853818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_ rw_with_rand_reset.2745853818 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1245864976 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 34070957 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245864976 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1245864976 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.663001327 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 22170975 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663001327 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.663001327 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.605057725 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 88913747 ps |
| CPU time | 1.18 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:18 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605057725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.605057725 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.215355962 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 15513216 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:18 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215355962 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.215355962 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3496094923 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 486167335 ps |
| CPU time | 2.63 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:23 PM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496094923 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3496094923 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1759658973 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 265658738 ps |
| CPU time | 1.36 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:18 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759658973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.1759658973 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3835147771 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 100557948 ps |
| CPU time | 2.5 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:19 PM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835147771 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.3835 147771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.963521140 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 136660437 ps |
| CPU time | 3.43 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963521140 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.963521140 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1428224528 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 157171724 ps |
| CPU time | 2.41 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:20 PM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428224528 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.1428224528 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3607934872 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 24016491 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607934872 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3607934872 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.365313295 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 24993382 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365313295 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.365313295 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1362289780 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 11872723 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362289780 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1362289780 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.458278901 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 15143288 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 11:18:38 PM UTC 24 |
| Finished | Oct 02 11:18:41 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458278901 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.458278901 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2632439566 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 14240551 ps |
| CPU time | 0.81 seconds |
| Started | Oct 02 11:18:40 PM UTC 24 |
| Finished | Oct 02 11:18:55 PM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632439566 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2632439566 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2032444253 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 137889388 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 11:18:40 PM UTC 24 |
| Finished | Oct 02 11:18:55 PM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032444253 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2032444253 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2954088690 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 35297044 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 11:18:40 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954088690 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2954088690 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3274275847 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 18504672 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 11:18:40 PM UTC 24 |
| Finished | Oct 02 11:18:55 PM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274275847 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3274275847 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3729335399 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 20021584 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 11:18:40 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729335399 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3729335399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.659055276 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 18587426 ps |
| CPU time | 0.87 seconds |
| Started | Oct 02 11:18:40 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659055276 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.659055276 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.1927019390 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 136067684 ps |
| CPU time | 3.93 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:25 PM UTC 24 |
| Peak memory | 226120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927019390 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1927019390 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.1736341963 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 287190338 ps |
| CPU time | 6.97 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:28 PM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736341963 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1736341963 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.3409701341 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 25119307 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409701341 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3409701341 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2333194840 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 147411861 ps |
| CPU time | 1.47 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 228596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2333194840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_ rw_with_rand_reset.2333194840 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.4006536071 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 38809409 ps |
| CPU time | 1.13 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006536071 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4006536071 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2345875068 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 120861287 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 224304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345875068 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2345875068 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.655004120 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 61727330 ps |
| CPU time | 1.12 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655004120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.655004120 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3577189579 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 16519858 ps |
| CPU time | 0.68 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577189579 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3577189579 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2788593828 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 100356130 ps |
| CPU time | 2.29 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:23 PM UTC 24 |
| Peak memory | 226128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788593828 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2788593828 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3625935001 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 361168068 ps |
| CPU time | 1.25 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625935001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.3625935001 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1313136618 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 114681284 ps |
| CPU time | 1.45 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313136618 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.1313 136618 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1868355643 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 49936760 ps |
| CPU time | 2.6 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:23 PM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868355643 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1868355643 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1200158353 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1079096066 ps |
| CPU time | 5.01 seconds |
| Started | Oct 02 11:18:16 PM UTC 24 |
| Finished | Oct 02 11:18:26 PM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200158353 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1200158353 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2972491943 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 24620048 ps |
| CPU time | 0.81 seconds |
| Started | Oct 02 11:18:40 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972491943 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2972491943 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1734205989 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 13458787 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 11:18:41 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734205989 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1734205989 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2617205647 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 38789157 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 11:18:41 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617205647 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2617205647 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3249810870 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 46486607 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249810870 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3249810870 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1055599124 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 21506710 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055599124 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1055599124 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1123539376 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 30555752 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123539376 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1123539376 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2706690267 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 18767595 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706690267 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2706690267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2491788283 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 19327354 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491788283 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2491788283 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.587001840 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 13771822 ps |
| CPU time | 1 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587001840 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.587001840 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1250551753 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 49562698 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250551753 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1250551753 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.2352539921 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 75748211 ps |
| CPU time | 3.69 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:28 PM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352539921 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2352539921 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2551797101 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 297424142 ps |
| CPU time | 13.51 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:45 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551797101 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2551797101 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.1587590157 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 100863499 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587590157 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1587590157 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3480663416 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 526194171 ps |
| CPU time | 2.06 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3480663416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_ rw_with_rand_reset.3480663416 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2006203696 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 16947260 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006203696 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2006203696 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.306898043 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 17091619 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306898043 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.306898043 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.1083572170 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 169742792 ps |
| CPU time | 1.4 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083572170 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.1083572170 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.2050123271 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 13313797 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050123271 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2050123271 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1100690562 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 173748992 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100690562 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.1100690562 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1312902675 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 128867308 ps |
| CPU time | 1.53 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 228592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312902675 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.1312 902675 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.4114209208 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 118320567 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:23 PM UTC 24 |
| Peak memory | 224572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114209208 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.4114209208 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.496898789 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 12966895 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496898789 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.496898789 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2532961843 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 52591259 ps |
| CPU time | 0.81 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532961843 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2532961843 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3477923072 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 134689608 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:03 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477923072 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3477923072 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.75206173 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 17889325 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:02 PM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75206173 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.75206173 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.709847966 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 13277494 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:02 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709847966 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.709847966 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2851551896 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 20547421 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:02 PM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851551896 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2851551896 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.334689859 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 24722997 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:02 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334689859 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.334689859 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.595963117 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 44594438 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:02 PM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595963117 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.595963117 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1811425522 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 15833281 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:02 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811425522 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1811425522 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3690551287 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 21869690 ps |
| CPU time | 0.79 seconds |
| Started | Oct 02 11:18:43 PM UTC 24 |
| Finished | Oct 02 11:19:02 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690551287 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3690551287 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1966168107 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 40930566 ps |
| CPU time | 1.41 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:21 PM UTC 24 |
| Peak memory | 230644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1966168107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_ rw_with_rand_reset.1966168107 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.2432488047 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 87258312 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:20 PM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432488047 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2432488047 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.3364599474 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 17927592 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364599474 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3364599474 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.565951058 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 103742495 ps |
| CPU time | 2.32 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:22 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565951058 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.565951058 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4056435335 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 165248132 ps |
| CPU time | 1.25 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056435335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.4056435335 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2584035990 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 41136380 ps |
| CPU time | 1.47 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 228596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584035990 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.2584 035990 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.231637597 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 291568185 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:34 PM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231637597 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.231637597 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1112554847 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 202513884 ps |
| CPU time | 3.55 seconds |
| Started | Oct 02 11:18:17 PM UTC 24 |
| Finished | Oct 02 11:18:35 PM UTC 24 |
| Peak memory | 226124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112554847 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1112554847 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2495677802 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 163810640 ps |
| CPU time | 2.14 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 230736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2495677802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_ rw_with_rand_reset.2495677802 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.416560826 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 16443307 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:30 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416560826 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.416560826 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.1145045388 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 11689328 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:30 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145045388 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1145045388 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.551881453 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 87056916 ps |
| CPU time | 2.29 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551881453 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.551881453 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.838190359 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 45873216 ps |
| CPU time | 1.2 seconds |
| Started | Oct 02 11:18:20 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838190359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.838190359 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1969012610 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 455935625 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:31 PM UTC 24 |
| Peak memory | 228592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969012610 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.1969 012610 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.2808104667 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 111227138 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808104667 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2808104667 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.638427804 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 277864503 ps |
| CPU time | 3.9 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638427804 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.638427804 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1225245344 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 84725859 ps |
| CPU time | 1.61 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1225245344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_ rw_with_rand_reset.1225245344 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.4151338799 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 30356380 ps |
| CPU time | 1 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151338799 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.4151338799 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3694112892 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 62457558 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694112892 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3694112892 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3738298457 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 40563295 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738298457 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3738298457 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.67051898 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 178131300 ps |
| CPU time | 1.89 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:31 PM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67051898 -assert nopostproc + UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.67051898 +enable_masking=1 +sw _key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3054793182 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 45842296 ps |
| CPU time | 2.07 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 226280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054793182 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.3054 793182 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1584417376 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 131490265 ps |
| CPU time | 3.12 seconds |
| Started | Oct 02 11:18:21 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584417376 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1584417376 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1133708530 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 173712044 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 11:18:22 PM UTC 24 |
| Finished | Oct 02 11:18:34 PM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133708530 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1133708530 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2899906577 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 79962543 ps |
| CPU time | 2.14 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2899906577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_ rw_with_rand_reset.2899906577 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.696835534 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 19373145 ps |
| CPU time | 1.12 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696835534 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.696835534 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1392874670 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 39516312 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392874670 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1392874670 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3371033512 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 332918714 ps |
| CPU time | 1.37 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371033512 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.3371033512 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1056898245 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 65221517 ps |
| CPU time | 1.01 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056898245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1056898245 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1687499722 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 94333207 ps |
| CPU time | 1.57 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687499722 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.1687 499722 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1021558336 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 149587961 ps |
| CPU time | 3.97 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:35 PM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021558336 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1021558336 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1486852170 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 145060196 ps |
| CPU time | 2.84 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:34 PM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486852170 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.1486852170 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.673224209 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 171467098 ps |
| CPU time | 1.77 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 226552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=673224209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_r w_with_rand_reset.673224209 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.826647168 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 33410189 ps |
| CPU time | 1.17 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826647168 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.826647168 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4088029142 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 28146939 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:32 PM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088029142 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.4088029142 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3667248435 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 87262631 ps |
| CPU time | 2.03 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:34 PM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667248435 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3667248435 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1481395242 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 50859450 ps |
| CPU time | 1.29 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481395242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.1481395242 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4129870287 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 69207282 ps |
| CPU time | 2.01 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 230576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129870287 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.4129 870287 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.555214909 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 408556411 ps |
| CPU time | 1.77 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:33 PM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555214909 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.555214909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3546125504 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 383543197 ps |
| CPU time | 3.81 seconds |
| Started | Oct 02 11:18:23 PM UTC 24 |
| Finished | Oct 02 11:18:35 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546125504 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.3546125504 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_app.1005447473 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3595934030 ps |
| CPU time | 26.62 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:04:15 AM UTC 24 |
| Peak memory | 246824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005447473 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1005447473 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.3272230372 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 57859538954 ps |
| CPU time | 674.92 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:15:10 AM UTC 24 |
| Peak memory | 254948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272230372 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3272230372 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.535251689 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1615884865 ps |
| CPU time | 16.19 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:04:06 AM UTC 24 |
| Peak memory | 236104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535251689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.535251689 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.267606292 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2249704247 ps |
| CPU time | 15.57 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:04:06 AM UTC 24 |
| Peak memory | 235584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267606292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.267606292 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2835614416 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 9994273086 ps |
| CPU time | 268.26 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:08:21 AM UTC 24 |
| Peak memory | 298024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835614416 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2835614416 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.2115028543 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 67521834 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:03:52 AM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115028543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2115028543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.1485843004 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 20399698124 ps |
| CPU time | 2070.22 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:38:39 AM UTC 24 |
| Peak memory | 1389476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485843004 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1485843004 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.1403585832 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11887631498 ps |
| CPU time | 367.85 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:10:00 AM UTC 24 |
| Peak memory | 484264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403585832 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1403585832 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.1484261950 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 7010005333 ps |
| CPU time | 90.85 seconds |
| Started | Oct 03 02:03:45 AM UTC 24 |
| Finished | Oct 03 02:05:18 AM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484261950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1484261950 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.3541236250 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 168237157920 ps |
| CPU time | 2052.87 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:38:30 AM UTC 24 |
| Peak memory | 1158460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541236250 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3541236250 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.3945110404 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 126845216 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:03:50 AM UTC 24 |
| Peak memory | 236480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945110404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.3945110404 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3808469100 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 118177387 ps |
| CPU time | 2.66 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:03:51 AM UTC 24 |
| Peak memory | 236632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808469100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3808469100 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.68571818 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 328855344571 ps |
| CPU time | 3253.28 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:58:40 AM UTC 24 |
| Peak memory | 3175244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68571818 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.68571818 +enable_m asking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.4085029624 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1929760594 ps |
| CPU time | 46.45 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:04:35 AM UTC 24 |
| Peak memory | 256884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085029624 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.4085029624 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1221109749 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 27827932723 ps |
| CPU time | 1481.64 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:28:46 AM UTC 24 |
| Peak memory | 914276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221109749 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1221109749 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.1834131662 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 12942474966 ps |
| CPU time | 279.1 seconds |
| Started | Oct 03 02:03:47 AM UTC 24 |
| Finished | Oct 03 02:08:30 AM UTC 24 |
| Peak memory | 283872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834131662 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1834131662 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.2045231548 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 47794423 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 02:04:17 AM UTC 24 |
| Finished | Oct 03 02:04:19 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045231548 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2045231548 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_app.2401881955 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 35178720250 ps |
| CPU time | 250.79 seconds |
| Started | Oct 03 02:04:05 AM UTC 24 |
| Finished | Oct 03 02:08:20 AM UTC 24 |
| Peak memory | 412760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401881955 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2401881955 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.592436704 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 19699517669 ps |
| CPU time | 234.02 seconds |
| Started | Oct 03 02:04:06 AM UTC 24 |
| Finished | Oct 03 02:08:03 AM UTC 24 |
| Peak memory | 308248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592436704 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.592436704 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.33501348 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 72593970864 ps |
| CPU time | 1929.66 seconds |
| Started | Oct 03 02:03:51 AM UTC 24 |
| Finished | Oct 03 02:36:28 AM UTC 24 |
| Peak memory | 277416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33501348 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.33501348 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3196407789 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 298405221 ps |
| CPU time | 4.3 seconds |
| Started | Oct 03 02:04:13 AM UTC 24 |
| Finished | Oct 03 02:04:18 AM UTC 24 |
| Peak memory | 234796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196407789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3196407789 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.3411855330 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13137343874 ps |
| CPU time | 208.72 seconds |
| Started | Oct 03 02:04:07 AM UTC 24 |
| Finished | Oct 03 02:07:39 AM UTC 24 |
| Peak memory | 304412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411855330 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.3411855330 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_error.595382011 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12736671069 ps |
| CPU time | 474.41 seconds |
| Started | Oct 03 02:04:07 AM UTC 24 |
| Finished | Oct 03 02:12:08 AM UTC 24 |
| Peak memory | 400476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595382011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.595382011 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.1262858591 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 53876686 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 02:04:13 AM UTC 24 |
| Finished | Oct 03 02:04:16 AM UTC 24 |
| Peak memory | 234588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262858591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1262858591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.362851828 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3249099997 ps |
| CPU time | 98.68 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:05:30 AM UTC 24 |
| Peak memory | 279824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362851828 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.362851828 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.182764011 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 11173159915 ps |
| CPU time | 416.25 seconds |
| Started | Oct 03 02:04:07 AM UTC 24 |
| Finished | Oct 03 02:11:09 AM UTC 24 |
| Peak memory | 347556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182764011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.182764011 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.3768658992 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 18187660007 ps |
| CPU time | 59.33 seconds |
| Started | Oct 03 02:04:16 AM UTC 24 |
| Finished | Oct 03 02:05:17 AM UTC 24 |
| Peak memory | 288872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768658992 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3768658992 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.1789800855 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 42311480728 ps |
| CPU time | 238.57 seconds |
| Started | Oct 03 02:03:51 AM UTC 24 |
| Finished | Oct 03 02:07:53 AM UTC 24 |
| Peak memory | 443420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789800855 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1789800855 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.4091805030 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3717145047 ps |
| CPU time | 20.86 seconds |
| Started | Oct 03 02:03:49 AM UTC 24 |
| Finished | Oct 03 02:04:12 AM UTC 24 |
| Peak memory | 236496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091805030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.4091805030 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.664562592 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 95131579 ps |
| CPU time | 4.9 seconds |
| Started | Oct 03 02:03:54 AM UTC 24 |
| Finished | Oct 03 02:04:00 AM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664562592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.664562592 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.2378373236 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2262160199 ps |
| CPU time | 52.2 seconds |
| Started | Oct 03 02:03:51 AM UTC 24 |
| Finished | Oct 03 02:04:45 AM UTC 24 |
| Peak memory | 236300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378373236 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2378373236 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.2223435030 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7860025585 ps |
| CPU time | 50.54 seconds |
| Started | Oct 03 02:03:51 AM UTC 24 |
| Finished | Oct 03 02:04:43 AM UTC 24 |
| Peak memory | 257008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223435030 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2223435030 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.3012534039 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1935134039 ps |
| CPU time | 52.13 seconds |
| Started | Oct 03 02:03:52 AM UTC 24 |
| Finished | Oct 03 02:04:46 AM UTC 24 |
| Peak memory | 242552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012534039 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3012534039 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.2402627033 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1876728982 ps |
| CPU time | 23.29 seconds |
| Started | Oct 03 02:03:52 AM UTC 24 |
| Finished | Oct 03 02:04:17 AM UTC 24 |
| Peak memory | 236404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402627033 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2402627033 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.2655809918 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 261761527714 ps |
| CPU time | 3262.55 seconds |
| Started | Oct 03 02:03:52 AM UTC 24 |
| Finished | Oct 03 02:58:55 AM UTC 24 |
| Peak memory | 3613524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655809918 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2655809918 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1602795813 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 329412762188 ps |
| CPU time | 2542.89 seconds |
| Started | Oct 03 02:03:52 AM UTC 24 |
| Finished | Oct 03 02:46:42 AM UTC 24 |
| Peak memory | 2962420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602795813 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1602795813 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.3825687560 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 20544170 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 02:34:26 AM UTC 24 |
| Finished | Oct 03 02:34:28 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825687560 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3825687560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_app.913865308 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 18844459188 ps |
| CPU time | 244.07 seconds |
| Started | Oct 03 02:33:20 AM UTC 24 |
| Finished | Oct 03 02:37:28 AM UTC 24 |
| Peak memory | 396284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913865308 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.913865308 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.1062084691 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 21882964269 ps |
| CPU time | 1227.45 seconds |
| Started | Oct 03 02:33:00 AM UTC 24 |
| Finished | Oct 03 02:53:43 AM UTC 24 |
| Peak memory | 265260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062084691 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1062084691 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.2429221526 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 410554836 ps |
| CPU time | 22.82 seconds |
| Started | Oct 03 02:33:57 AM UTC 24 |
| Finished | Oct 03 02:34:21 AM UTC 24 |
| Peak memory | 236176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429221526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2429221526 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.75583817 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 51707164 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 02:34:21 AM UTC 24 |
| Finished | Oct 03 02:34:24 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75583817 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.75583817 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.745723760 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 340731655 ps |
| CPU time | 5.95 seconds |
| Started | Oct 03 02:33:39 AM UTC 24 |
| Finished | Oct 03 02:33:46 AM UTC 24 |
| Peak memory | 232716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745723760 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.745723760 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_error.2997153560 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 56348121880 ps |
| CPU time | 511.63 seconds |
| Started | Oct 03 02:33:41 AM UTC 24 |
| Finished | Oct 03 02:42:20 AM UTC 24 |
| Peak memory | 613356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997153560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2997153560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.1440557468 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3100755108 ps |
| CPU time | 6.74 seconds |
| Started | Oct 03 02:33:48 AM UTC 24 |
| Finished | Oct 03 02:33:55 AM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440557468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1440557468 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.1230312377 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 139840935 ps |
| CPU time | 2.2 seconds |
| Started | Oct 03 02:34:22 AM UTC 24 |
| Finished | Oct 03 02:34:25 AM UTC 24 |
| Peak memory | 232528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230312377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1230312377 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.3522987194 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 24299280522 ps |
| CPU time | 997.95 seconds |
| Started | Oct 03 02:32:40 AM UTC 24 |
| Finished | Oct 03 02:49:31 AM UTC 24 |
| Peak memory | 1299624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522987194 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.3522987194 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.840219615 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 30025319719 ps |
| CPU time | 251.26 seconds |
| Started | Oct 03 02:32:59 AM UTC 24 |
| Finished | Oct 03 02:37:14 AM UTC 24 |
| Peak memory | 435236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840219615 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.840219615 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.3540720861 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2810672387 ps |
| CPU time | 53.03 seconds |
| Started | Oct 03 02:32:25 AM UTC 24 |
| Finished | Oct 03 02:33:19 AM UTC 24 |
| Peak memory | 236564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540720861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3540720861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.36112402 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 53923853 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 02:34:25 AM UTC 24 |
| Finished | Oct 03 02:34:30 AM UTC 24 |
| Peak memory | 230576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36112402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.36112402 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.1448557928 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 379457641 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 02:36:41 AM UTC 24 |
| Finished | Oct 03 02:36:44 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448557928 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1448557928 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_app.1584285775 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 12501801827 ps |
| CPU time | 196.54 seconds |
| Started | Oct 03 02:34:48 AM UTC 24 |
| Finished | Oct 03 02:38:09 AM UTC 24 |
| Peak memory | 336912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584285775 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1584285775 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.503508032 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 7084288291 ps |
| CPU time | 363.74 seconds |
| Started | Oct 03 02:34:30 AM UTC 24 |
| Finished | Oct 03 02:40:39 AM UTC 24 |
| Peak memory | 244708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503508032 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.503508032 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2496629165 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 976309805 ps |
| CPU time | 33.85 seconds |
| Started | Oct 03 02:36:10 AM UTC 24 |
| Finished | Oct 03 02:36:45 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496629165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2496629165 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.2947518981 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 6318544233 ps |
| CPU time | 54.47 seconds |
| Started | Oct 03 02:36:13 AM UTC 24 |
| Finished | Oct 03 02:37:09 AM UTC 24 |
| Peak memory | 236252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947518981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2947518981 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.4104873867 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 60911311504 ps |
| CPU time | 284.76 seconds |
| Started | Oct 03 02:35:12 AM UTC 24 |
| Finished | Oct 03 02:40:01 AM UTC 24 |
| Peak memory | 388148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104873867 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.4104873867 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_error.191168922 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 9985198996 ps |
| CPU time | 189.92 seconds |
| Started | Oct 03 02:35:43 AM UTC 24 |
| Finished | Oct 03 02:38:56 AM UTC 24 |
| Peak memory | 312300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191168922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.191168922 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.645496355 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5968974423 ps |
| CPU time | 18.79 seconds |
| Started | Oct 03 02:35:52 AM UTC 24 |
| Finished | Oct 03 02:36:12 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645496355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.645496355 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.1001620219 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 112647909990 ps |
| CPU time | 2200.3 seconds |
| Started | Oct 03 02:34:29 AM UTC 24 |
| Finished | Oct 03 03:11:34 AM UTC 24 |
| Peak memory | 2456552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001620219 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.1001620219 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.3375523524 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 4048370692 ps |
| CPU time | 207.56 seconds |
| Started | Oct 03 02:34:30 AM UTC 24 |
| Finished | Oct 03 02:38:01 AM UTC 24 |
| Peak memory | 345128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375523524 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3375523524 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.1678687112 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1504914312 ps |
| CPU time | 40.59 seconds |
| Started | Oct 03 02:34:28 AM UTC 24 |
| Finished | Oct 03 02:35:10 AM UTC 24 |
| Peak memory | 236700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678687112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1678687112 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.675868946 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 53136172051 ps |
| CPU time | 2079.14 seconds |
| Started | Oct 03 02:36:32 AM UTC 24 |
| Finished | Oct 03 03:11:36 AM UTC 24 |
| Peak memory | 1183036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675868946 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.675868946 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.919722774 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 37218701 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 02:38:25 AM UTC 24 |
| Finished | Oct 03 02:38:27 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919722774 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.919722774 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_app.665217495 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 14325005925 ps |
| CPU time | 409.26 seconds |
| Started | Oct 03 02:37:29 AM UTC 24 |
| Finished | Oct 03 02:44:24 AM UTC 24 |
| Peak memory | 498652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665217495 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.665217495 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.1738073669 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 30441037743 ps |
| CPU time | 1571.22 seconds |
| Started | Oct 03 02:37:15 AM UTC 24 |
| Finished | Oct 03 03:03:47 AM UTC 24 |
| Peak memory | 269292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738073669 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1738073669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.844070271 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 36703857 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 02:38:13 AM UTC 24 |
| Finished | Oct 03 02:38:16 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844070271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.844070271 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3994085717 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 34291155 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 02:38:17 AM UTC 24 |
| Finished | Oct 03 02:38:19 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994085717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3994085717 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.3160135262 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 56140807116 ps |
| CPU time | 186.57 seconds |
| Started | Oct 03 02:37:44 AM UTC 24 |
| Finished | Oct 03 02:40:54 AM UTC 24 |
| Peak memory | 353324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160135262 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3160135262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_error.707549269 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 12934546727 ps |
| CPU time | 333.01 seconds |
| Started | Oct 03 02:38:02 AM UTC 24 |
| Finished | Oct 03 02:43:40 AM UTC 24 |
| Peak memory | 355372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707549269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.707549269 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.3933949110 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1411346264 ps |
| CPU time | 5.81 seconds |
| Started | Oct 03 02:38:10 AM UTC 24 |
| Finished | Oct 03 02:38:17 AM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933949110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3933949110 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.1571617304 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2007756165 ps |
| CPU time | 13.31 seconds |
| Started | Oct 03 02:38:18 AM UTC 24 |
| Finished | Oct 03 02:38:32 AM UTC 24 |
| Peak memory | 246768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571617304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1571617304 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.1895778654 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 161595198388 ps |
| CPU time | 4166.35 seconds |
| Started | Oct 03 02:36:47 AM UTC 24 |
| Finished | Oct 03 03:46:57 AM UTC 24 |
| Peak memory | 4330628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895778654 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.1895778654 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.584164959 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2194414926 ps |
| CPU time | 237 seconds |
| Started | Oct 03 02:37:10 AM UTC 24 |
| Finished | Oct 03 02:41:11 AM UTC 24 |
| Peak memory | 289828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584164959 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.584164959 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.3688943487 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 6473255129 ps |
| CPU time | 86.23 seconds |
| Started | Oct 03 02:36:45 AM UTC 24 |
| Finished | Oct 03 02:38:13 AM UTC 24 |
| Peak memory | 236824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688943487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3688943487 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.37811863 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 75833490510 ps |
| CPU time | 1471.8 seconds |
| Started | Oct 03 02:38:20 AM UTC 24 |
| Finished | Oct 03 03:03:10 AM UTC 24 |
| Peak memory | 646544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37811863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.37811863 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.2251180900 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 18677923 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 02:39:44 AM UTC 24 |
| Finished | Oct 03 02:39:47 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251180900 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2251180900 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_app.705161587 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3784436238 ps |
| CPU time | 98.99 seconds |
| Started | Oct 03 02:38:39 AM UTC 24 |
| Finished | Oct 03 02:40:20 AM UTC 24 |
| Peak memory | 295968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705161587 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.705161587 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.772852471 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 555478721 ps |
| CPU time | 30.74 seconds |
| Started | Oct 03 02:38:38 AM UTC 24 |
| Finished | Oct 03 02:39:10 AM UTC 24 |
| Peak memory | 236448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772852471 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.772852471 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2877280477 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 132276390 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 02:39:36 AM UTC 24 |
| Finished | Oct 03 02:39:39 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877280477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2877280477 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.3811827885 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 87256987 ps |
| CPU time | 1 seconds |
| Started | Oct 03 02:39:39 AM UTC 24 |
| Finished | Oct 03 02:39:41 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811827885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3811827885 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.2144956946 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 28230535836 ps |
| CPU time | 137.35 seconds |
| Started | Oct 03 02:38:56 AM UTC 24 |
| Finished | Oct 03 02:41:16 AM UTC 24 |
| Peak memory | 306212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144956946 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2144956946 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_error.1500389059 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 480757897 ps |
| CPU time | 46.59 seconds |
| Started | Oct 03 02:39:11 AM UTC 24 |
| Finished | Oct 03 02:39:59 AM UTC 24 |
| Peak memory | 262720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500389059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1500389059 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.1966215025 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1096943244 ps |
| CPU time | 12.59 seconds |
| Started | Oct 03 02:39:21 AM UTC 24 |
| Finished | Oct 03 02:39:34 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966215025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1966215025 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.2168473166 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 148014389 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 02:39:40 AM UTC 24 |
| Finished | Oct 03 02:39:43 AM UTC 24 |
| Peak memory | 232416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168473166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2168473166 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.3145588388 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3030254064 ps |
| CPU time | 303.5 seconds |
| Started | Oct 03 02:38:31 AM UTC 24 |
| Finished | Oct 03 02:43:39 AM UTC 24 |
| Peak memory | 400424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145588388 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.3145588388 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.1336846175 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 24989425521 ps |
| CPU time | 311.84 seconds |
| Started | Oct 03 02:38:33 AM UTC 24 |
| Finished | Oct 03 02:43:49 AM UTC 24 |
| Peak memory | 492584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336846175 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1336846175 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.252973229 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 14135783466 ps |
| CPU time | 69.11 seconds |
| Started | Oct 03 02:38:28 AM UTC 24 |
| Finished | Oct 03 02:39:39 AM UTC 24 |
| Peak memory | 236632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252973229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.252973229 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.4280413669 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 30011494756 ps |
| CPU time | 748.39 seconds |
| Started | Oct 03 02:39:42 AM UTC 24 |
| Finished | Oct 03 02:52:20 AM UTC 24 |
| Peak memory | 441728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280413669 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.4280413669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.3040161814 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 56981096 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 02:40:48 AM UTC 24 |
| Finished | Oct 03 02:40:51 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040161814 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3040161814 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_app.29029047 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4919542223 ps |
| CPU time | 247.8 seconds |
| Started | Oct 03 02:40:18 AM UTC 24 |
| Finished | Oct 03 02:44:29 AM UTC 24 |
| Peak memory | 300116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29029047 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.29029047 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.1433545850 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 26051630239 ps |
| CPU time | 1419.22 seconds |
| Started | Oct 03 02:40:01 AM UTC 24 |
| Finished | Oct 03 03:03:59 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433545850 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1433545850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.4159461208 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 92291123 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 02:40:44 AM UTC 24 |
| Finished | Oct 03 02:40:46 AM UTC 24 |
| Peak memory | 228164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159461208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.4159461208 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.2243579347 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 95770885 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 02:40:44 AM UTC 24 |
| Finished | Oct 03 02:40:47 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243579347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2243579347 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.3185372047 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1817842782 ps |
| CPU time | 8.8 seconds |
| Started | Oct 03 02:40:22 AM UTC 24 |
| Finished | Oct 03 02:40:32 AM UTC 24 |
| Peak memory | 236712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185372047 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3185372047 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_error.491111153 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 9511167618 ps |
| CPU time | 373.89 seconds |
| Started | Oct 03 02:40:33 AM UTC 24 |
| Finished | Oct 03 02:46:52 AM UTC 24 |
| Peak memory | 377948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491111153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.491111153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.2457198974 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1319655725 ps |
| CPU time | 6.82 seconds |
| Started | Oct 03 02:40:40 AM UTC 24 |
| Finished | Oct 03 02:40:48 AM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457198974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2457198974 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.146359003 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1558762256 ps |
| CPU time | 10.63 seconds |
| Started | Oct 03 02:40:47 AM UTC 24 |
| Finished | Oct 03 02:40:59 AM UTC 24 |
| Peak memory | 246692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146359003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.146359003 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.1953234599 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 23960446407 ps |
| CPU time | 2946.91 seconds |
| Started | Oct 03 02:39:49 AM UTC 24 |
| Finished | Oct 03 03:29:30 AM UTC 24 |
| Peak memory | 1649752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953234599 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.1953234599 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.3455025253 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 10616140182 ps |
| CPU time | 240.04 seconds |
| Started | Oct 03 02:39:59 AM UTC 24 |
| Finished | Oct 03 02:44:03 AM UTC 24 |
| Peak memory | 375844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455025253 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3455025253 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.3786256183 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1640089509 ps |
| CPU time | 54.77 seconds |
| Started | Oct 03 02:39:47 AM UTC 24 |
| Finished | Oct 03 02:40:44 AM UTC 24 |
| Peak memory | 236496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786256183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3786256183 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.1336782096 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 29393347979 ps |
| CPU time | 590.87 seconds |
| Started | Oct 03 02:40:47 AM UTC 24 |
| Finished | Oct 03 02:50:46 AM UTC 24 |
| Peak memory | 351624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336782096 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1336782096 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.3293170299 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 147195116 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 02:43:41 AM UTC 24 |
| Finished | Oct 03 02:43:43 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293170299 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3293170299 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_app.3651386416 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 23469167688 ps |
| CPU time | 406.94 seconds |
| Started | Oct 03 02:41:17 AM UTC 24 |
| Finished | Oct 03 02:48:10 AM UTC 24 |
| Peak memory | 345316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651386416 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3651386416 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.3482550098 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 54883980639 ps |
| CPU time | 1295.86 seconds |
| Started | Oct 03 02:41:12 AM UTC 24 |
| Finished | Oct 03 03:03:03 AM UTC 24 |
| Peak memory | 271596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482550098 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.3482550098 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1248089697 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1458833348 ps |
| CPU time | 61.96 seconds |
| Started | Oct 03 02:42:34 AM UTC 24 |
| Finished | Oct 03 02:43:37 AM UTC 24 |
| Peak memory | 248732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248089697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1248089697 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.2053666934 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 213062390 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 02:43:38 AM UTC 24 |
| Finished | Oct 03 02:43:40 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053666934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2053666934 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.1270834688 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 41287129554 ps |
| CPU time | 287.87 seconds |
| Started | Oct 03 02:41:19 AM UTC 24 |
| Finished | Oct 03 02:46:11 AM UTC 24 |
| Peak memory | 412716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270834688 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1270834688 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_error.1043574768 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 15286838792 ps |
| CPU time | 529.39 seconds |
| Started | Oct 03 02:42:21 AM UTC 24 |
| Finished | Oct 03 02:51:18 AM UTC 24 |
| Peak memory | 633900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043574768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1043574768 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.414936210 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2575198004 ps |
| CPU time | 5.71 seconds |
| Started | Oct 03 02:42:26 AM UTC 24 |
| Finished | Oct 03 02:42:33 AM UTC 24 |
| Peak memory | 228676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414936210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.414936210 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.3775424135 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 66704796772 ps |
| CPU time | 1826.31 seconds |
| Started | Oct 03 02:40:55 AM UTC 24 |
| Finished | Oct 03 03:11:43 AM UTC 24 |
| Peak memory | 1252324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775424135 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.3775424135 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.28816746 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 745888597 ps |
| CPU time | 17.21 seconds |
| Started | Oct 03 02:41:00 AM UTC 24 |
| Finished | Oct 03 02:41:18 AM UTC 24 |
| Peak memory | 246688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28816746 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.28816746 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.3046141538 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 4693088411 ps |
| CPU time | 92.41 seconds |
| Started | Oct 03 02:40:51 AM UTC 24 |
| Finished | Oct 03 02:42:26 AM UTC 24 |
| Peak memory | 238612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046141538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3046141538 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.906194051 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 14221468465 ps |
| CPU time | 466.3 seconds |
| Started | Oct 03 02:43:40 AM UTC 24 |
| Finished | Oct 03 02:51:33 AM UTC 24 |
| Peak memory | 269676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906194051 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.906194051 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.1381069291 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 14003900 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 02:46:12 AM UTC 24 |
| Finished | Oct 03 02:46:14 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381069291 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1381069291 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_app.254786710 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 28441470853 ps |
| CPU time | 398.6 seconds |
| Started | Oct 03 02:44:21 AM UTC 24 |
| Finished | Oct 03 02:51:06 AM UTC 24 |
| Peak memory | 339176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254786710 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.254786710 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.2588669408 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4715944065 ps |
| CPU time | 463.43 seconds |
| Started | Oct 03 02:44:04 AM UTC 24 |
| Finished | Oct 03 02:51:53 AM UTC 24 |
| Peak memory | 252976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588669408 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2588669408 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3685031048 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 67124834 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 02:44:46 AM UTC 24 |
| Finished | Oct 03 02:44:49 AM UTC 24 |
| Peak memory | 228164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685031048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3685031048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.1829458898 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 341238101 ps |
| CPU time | 11.2 seconds |
| Started | Oct 03 02:44:49 AM UTC 24 |
| Finished | Oct 03 02:45:02 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829458898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1829458898 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.1228292374 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 53226131411 ps |
| CPU time | 291.51 seconds |
| Started | Oct 03 02:44:25 AM UTC 24 |
| Finished | Oct 03 02:49:21 AM UTC 24 |
| Peak memory | 353300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228292374 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1228292374 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_error.492356952 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 12654235753 ps |
| CPU time | 172.86 seconds |
| Started | Oct 03 02:44:30 AM UTC 24 |
| Finished | Oct 03 02:47:26 AM UTC 24 |
| Peak memory | 298216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492356952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.492356952 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.1527365985 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 37443589 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 02:44:42 AM UTC 24 |
| Finished | Oct 03 02:44:45 AM UTC 24 |
| Peak memory | 228344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527365985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1527365985 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.1680979105 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 130132322 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 02:45:02 AM UTC 24 |
| Finished | Oct 03 02:45:05 AM UTC 24 |
| Peak memory | 234576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680979105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1680979105 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.409631353 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 465934147770 ps |
| CPU time | 5211.92 seconds |
| Started | Oct 03 02:43:44 AM UTC 24 |
| Finished | Oct 03 04:11:38 AM UTC 24 |
| Peak memory | 4570252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409631353 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.409631353 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.1169191346 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 34651460661 ps |
| CPU time | 306.65 seconds |
| Started | Oct 03 02:43:51 AM UTC 24 |
| Finished | Oct 03 02:49:02 AM UTC 24 |
| Peak memory | 459756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169191346 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1169191346 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.3123486115 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1387136835 ps |
| CPU time | 33.63 seconds |
| Started | Oct 03 02:43:44 AM UTC 24 |
| Finished | Oct 03 02:44:19 AM UTC 24 |
| Peak memory | 236460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123486115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3123486115 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.188105240 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 12237766273 ps |
| CPU time | 1199.1 seconds |
| Started | Oct 03 02:45:06 AM UTC 24 |
| Finished | Oct 03 03:05:20 AM UTC 24 |
| Peak memory | 583084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188105240 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.188105240 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.705171946 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 23472499 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 02:48:30 AM UTC 24 |
| Finished | Oct 03 02:48:33 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705171946 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.705171946 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_app.1532435805 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1487676419 ps |
| CPU time | 48.32 seconds |
| Started | Oct 03 02:47:17 AM UTC 24 |
| Finished | Oct 03 02:48:07 AM UTC 24 |
| Peak memory | 254864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532435805 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1532435805 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.2622444417 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 15360329480 ps |
| CPU time | 426.56 seconds |
| Started | Oct 03 02:46:53 AM UTC 24 |
| Finished | Oct 03 02:54:06 AM UTC 24 |
| Peak memory | 242720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622444417 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2622444417 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.4006324032 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 47312044 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 02:48:19 AM UTC 24 |
| Finished | Oct 03 02:48:22 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006324032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4006324032 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.1431199934 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 102109497 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 02:48:23 AM UTC 24 |
| Finished | Oct 03 02:48:26 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431199934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1431199934 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2304065195 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4425766483 ps |
| CPU time | 130.1 seconds |
| Started | Oct 03 02:47:27 AM UTC 24 |
| Finished | Oct 03 02:49:39 AM UTC 24 |
| Peak memory | 283688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304065195 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2304065195 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_error.1998337316 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5899183973 ps |
| CPU time | 147.94 seconds |
| Started | Oct 03 02:48:08 AM UTC 24 |
| Finished | Oct 03 02:50:39 AM UTC 24 |
| Peak memory | 351184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998337316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1998337316 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.1946744848 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4034358341 ps |
| CPU time | 12.96 seconds |
| Started | Oct 03 02:48:11 AM UTC 24 |
| Finished | Oct 03 02:48:25 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946744848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1946744848 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.886790178 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 34641681 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 02:48:26 AM UTC 24 |
| Finished | Oct 03 02:48:29 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886790178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.886790178 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.3341426555 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 75817675948 ps |
| CPU time | 2339.02 seconds |
| Started | Oct 03 02:46:29 AM UTC 24 |
| Finished | Oct 03 03:25:55 AM UTC 24 |
| Peak memory | 1274920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341426555 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.3341426555 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.1423315015 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1141616672 ps |
| CPU time | 32.91 seconds |
| Started | Oct 03 02:46:42 AM UTC 24 |
| Finished | Oct 03 02:47:16 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423315015 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1423315015 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.1497908159 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1020067658 ps |
| CPU time | 11.83 seconds |
| Started | Oct 03 02:46:15 AM UTC 24 |
| Finished | Oct 03 02:46:28 AM UTC 24 |
| Peak memory | 236628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497908159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1497908159 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.1712835433 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 104804586224 ps |
| CPU time | 2010.64 seconds |
| Started | Oct 03 02:48:26 AM UTC 24 |
| Finished | Oct 03 03:22:21 AM UTC 24 |
| Peak memory | 646520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712835433 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1712835433 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.2593748716 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 70750255 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 02:51:04 AM UTC 24 |
| Finished | Oct 03 02:51:06 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593748716 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2593748716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_app.1189368669 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 359887845 ps |
| CPU time | 15.88 seconds |
| Started | Oct 03 02:49:37 AM UTC 24 |
| Finished | Oct 03 02:49:55 AM UTC 24 |
| Peak memory | 236468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189368669 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1189368669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.3925912361 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 11949891384 ps |
| CPU time | 1212.22 seconds |
| Started | Oct 03 02:49:32 AM UTC 24 |
| Finished | Oct 03 03:09:59 AM UTC 24 |
| Peak memory | 255020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925912361 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3925912361 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.1057958540 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1235855347 ps |
| CPU time | 53.08 seconds |
| Started | Oct 03 02:50:47 AM UTC 24 |
| Finished | Oct 03 02:51:41 AM UTC 24 |
| Peak memory | 236128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057958540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1057958540 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.485557218 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 31941256 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 02:50:56 AM UTC 24 |
| Finished | Oct 03 02:50:58 AM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485557218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.485557218 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.422553577 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 6195952153 ps |
| CPU time | 137.21 seconds |
| Started | Oct 03 02:49:40 AM UTC 24 |
| Finished | Oct 03 02:52:00 AM UTC 24 |
| Peak memory | 281640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422553577 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.422553577 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_error.3941162262 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 9399581057 ps |
| CPU time | 308.78 seconds |
| Started | Oct 03 02:49:55 AM UTC 24 |
| Finished | Oct 03 02:55:09 AM UTC 24 |
| Peak memory | 463980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941162262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3941162262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.2690735677 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4863811638 ps |
| CPU time | 14.02 seconds |
| Started | Oct 03 02:50:40 AM UTC 24 |
| Finished | Oct 03 02:50:55 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690735677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2690735677 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.3921067719 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 48222379 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 02:50:59 AM UTC 24 |
| Finished | Oct 03 02:51:02 AM UTC 24 |
| Peak memory | 232540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921067719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3921067719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1511413953 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 49283062616 ps |
| CPU time | 1973.85 seconds |
| Started | Oct 03 02:49:03 AM UTC 24 |
| Finished | Oct 03 03:22:20 AM UTC 24 |
| Peak memory | 2389080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511413953 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1511413953 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.2764648718 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2319371786 ps |
| CPU time | 209.73 seconds |
| Started | Oct 03 02:49:22 AM UTC 24 |
| Finished | Oct 03 02:52:55 AM UTC 24 |
| Peak memory | 308264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764648718 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2764648718 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.2532227447 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3281812138 ps |
| CPU time | 60.66 seconds |
| Started | Oct 03 02:48:34 AM UTC 24 |
| Finished | Oct 03 02:49:36 AM UTC 24 |
| Peak memory | 236844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532227447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2532227447 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.561012324 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 174331612116 ps |
| CPU time | 4610.38 seconds |
| Started | Oct 03 02:51:03 AM UTC 24 |
| Finished | Oct 03 04:08:51 AM UTC 24 |
| Peak memory | 1023284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561012324 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.561012324 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.420741765 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 18549548 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 02:52:32 AM UTC 24 |
| Finished | Oct 03 02:52:35 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420741765 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.420741765 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_app.1214774777 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 50287750062 ps |
| CPU time | 292.21 seconds |
| Started | Oct 03 02:51:43 AM UTC 24 |
| Finished | Oct 03 02:56:39 AM UTC 24 |
| Peak memory | 416804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214774777 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1214774777 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.1918283990 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 33870101961 ps |
| CPU time | 663.26 seconds |
| Started | Oct 03 02:51:34 AM UTC 24 |
| Finished | Oct 03 03:02:47 AM UTC 24 |
| Peak memory | 250912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918283990 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1918283990 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.2769921629 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 45623975 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 02:52:21 AM UTC 24 |
| Finished | Oct 03 02:52:23 AM UTC 24 |
| Peak memory | 228164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769921629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2769921629 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.55604059 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 24564371 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 02:52:24 AM UTC 24 |
| Finished | Oct 03 02:52:27 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55604059 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.55604059 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.55961154 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 9127490351 ps |
| CPU time | 320.44 seconds |
| Started | Oct 03 02:51:54 AM UTC 24 |
| Finished | Oct 03 02:57:19 AM UTC 24 |
| Peak memory | 328676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55961154 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.55961154 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_error.1383074170 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 19326457093 ps |
| CPU time | 467.54 seconds |
| Started | Oct 03 02:52:01 AM UTC 24 |
| Finished | Oct 03 02:59:55 AM UTC 24 |
| Peak memory | 363552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383074170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1383074170 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.4126116326 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2076465641 ps |
| CPU time | 7.04 seconds |
| Started | Oct 03 02:52:20 AM UTC 24 |
| Finished | Oct 03 02:52:28 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126116326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.4126116326 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.1679952778 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 160717152 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 02:52:28 AM UTC 24 |
| Finished | Oct 03 02:52:31 AM UTC 24 |
| Peak memory | 234056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679952778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1679952778 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.804662616 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 140795473673 ps |
| CPU time | 1324.03 seconds |
| Started | Oct 03 02:51:07 AM UTC 24 |
| Finished | Oct 03 03:13:27 AM UTC 24 |
| Peak memory | 1690656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804662616 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.804662616 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.4219751503 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 52427259736 ps |
| CPU time | 144.2 seconds |
| Started | Oct 03 02:51:19 AM UTC 24 |
| Finished | Oct 03 02:53:46 AM UTC 24 |
| Peak memory | 328732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219751503 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.4219751503 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.1659699095 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 10526882363 ps |
| CPU time | 71.09 seconds |
| Started | Oct 03 02:51:06 AM UTC 24 |
| Finished | Oct 03 02:52:19 AM UTC 24 |
| Peak memory | 236756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659699095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1659699095 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.495586833 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 10763180900 ps |
| CPU time | 522.79 seconds |
| Started | Oct 03 02:52:29 AM UTC 24 |
| Finished | Oct 03 03:01:19 AM UTC 24 |
| Peak memory | 324604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495586833 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.495586833 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.882056336 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 20415213 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:07:31 AM UTC 24 |
| Finished | Oct 03 02:07:33 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882056336 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.882056336 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_app.3682334291 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 29224971722 ps |
| CPU time | 272.56 seconds |
| Started | Oct 03 02:05:31 AM UTC 24 |
| Finished | Oct 03 02:10:08 AM UTC 24 |
| Peak memory | 367828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682334291 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3682334291 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.963965888 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 22188907549 ps |
| CPU time | 280.58 seconds |
| Started | Oct 03 02:05:31 AM UTC 24 |
| Finished | Oct 03 02:10:17 AM UTC 24 |
| Peak memory | 316368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963965888 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.963965888 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.1193819540 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 43468045047 ps |
| CPU time | 1145.89 seconds |
| Started | Oct 03 02:04:33 AM UTC 24 |
| Finished | Oct 03 02:23:53 AM UTC 24 |
| Peak memory | 252964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193819540 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.1193819540 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.3158658377 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 614020962 ps |
| CPU time | 10.82 seconds |
| Started | Oct 03 02:06:33 AM UTC 24 |
| Finished | Oct 03 02:06:45 AM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158658377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3158658377 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.2355827371 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 33292978 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 02:06:44 AM UTC 24 |
| Finished | Oct 03 02:06:47 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355827371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2355827371 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.2819174801 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7124354475 ps |
| CPU time | 317.37 seconds |
| Started | Oct 03 02:05:51 AM UTC 24 |
| Finished | Oct 03 02:11:13 AM UTC 24 |
| Peak memory | 328676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819174801 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.2819174801 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_error.1953251909 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 20696588991 ps |
| CPU time | 746.08 seconds |
| Started | Oct 03 02:05:51 AM UTC 24 |
| Finished | Oct 03 02:18:26 AM UTC 24 |
| Peak memory | 678956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953251909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1953251909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.3295941225 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 669310876 ps |
| CPU time | 9.46 seconds |
| Started | Oct 03 02:06:21 AM UTC 24 |
| Finished | Oct 03 02:06:31 AM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295941225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3295941225 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.1883372866 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 55473101 ps |
| CPU time | 2.74 seconds |
| Started | Oct 03 02:06:47 AM UTC 24 |
| Finished | Oct 03 02:06:51 AM UTC 24 |
| Peak memory | 234724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883372866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1883372866 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.378187816 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 56395413018 ps |
| CPU time | 3298.71 seconds |
| Started | Oct 03 02:04:19 AM UTC 24 |
| Finished | Oct 03 03:00:00 AM UTC 24 |
| Peak memory | 1756136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378187816 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.378187816 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.2807516471 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 16620022219 ps |
| CPU time | 261.58 seconds |
| Started | Oct 03 02:05:51 AM UTC 24 |
| Finished | Oct 03 02:10:16 AM UTC 24 |
| Peak memory | 324920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807516471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2807516471 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.2148430544 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2653718043 ps |
| CPU time | 46.4 seconds |
| Started | Oct 03 02:07:02 AM UTC 24 |
| Finished | Oct 03 02:07:50 AM UTC 24 |
| Peak memory | 278696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148430544 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2148430544 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.365807505 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 19264822646 ps |
| CPU time | 380.53 seconds |
| Started | Oct 03 02:04:20 AM UTC 24 |
| Finished | Oct 03 02:10:46 AM UTC 24 |
| Peak memory | 496596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365807505 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.365807505 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.1896440116 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 219697574417 ps |
| CPU time | 1735.83 seconds |
| Started | Oct 03 02:06:51 AM UTC 24 |
| Finished | Oct 03 02:36:09 AM UTC 24 |
| Peak memory | 1138252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896440116 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1896440116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.2581188669 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 196337635 ps |
| CPU time | 3.41 seconds |
| Started | Oct 03 02:05:19 AM UTC 24 |
| Finished | Oct 03 02:05:23 AM UTC 24 |
| Peak memory | 236404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581188669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.2581188669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.1517802684 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 119820523 ps |
| CPU time | 4.72 seconds |
| Started | Oct 03 02:05:24 AM UTC 24 |
| Finished | Oct 03 02:05:30 AM UTC 24 |
| Peak memory | 236404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517802684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1517802684 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.2218542100 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2917205978 ps |
| CPU time | 72.34 seconds |
| Started | Oct 03 02:04:35 AM UTC 24 |
| Finished | Oct 03 02:05:50 AM UTC 24 |
| Peak memory | 261052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218542100 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2218542100 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.1239494408 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 90518362099 ps |
| CPU time | 3028.29 seconds |
| Started | Oct 03 02:04:45 AM UTC 24 |
| Finished | Oct 03 02:55:50 AM UTC 24 |
| Peak memory | 2964576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239494408 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1239494408 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.2048543109 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 54637224251 ps |
| CPU time | 1778.18 seconds |
| Started | Oct 03 02:04:46 AM UTC 24 |
| Finished | Oct 03 02:34:47 AM UTC 24 |
| Peak memory | 914596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048543109 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2048543109 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.1547744628 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 21317642251 ps |
| CPU time | 1208.87 seconds |
| Started | Oct 03 02:04:47 AM UTC 24 |
| Finished | Oct 03 02:25:10 AM UTC 24 |
| Peak memory | 713892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547744628 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1547744628 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3960108870 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 42221181416 ps |
| CPU time | 272.85 seconds |
| Started | Oct 03 02:04:56 AM UTC 24 |
| Finished | Oct 03 02:09:33 AM UTC 24 |
| Peak memory | 445616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960108870 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3960108870 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.1761559338 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 12529825623 ps |
| CPU time | 162.23 seconds |
| Started | Oct 03 02:05:18 AM UTC 24 |
| Finished | Oct 03 02:08:03 AM UTC 24 |
| Peak memory | 267248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761559338 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1761559338 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.3404663260 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 43217802 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 02:55:50 AM UTC 24 |
| Finished | Oct 03 02:55:52 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404663260 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3404663260 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_app.1219588029 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3453525431 ps |
| CPU time | 236.29 seconds |
| Started | Oct 03 02:53:44 AM UTC 24 |
| Finished | Oct 03 02:57:44 AM UTC 24 |
| Peak memory | 306160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219588029 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1219588029 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.1705816401 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 201696884995 ps |
| CPU time | 790.3 seconds |
| Started | Oct 03 02:53:36 AM UTC 24 |
| Finished | Oct 03 03:06:57 AM UTC 24 |
| Peak memory | 259116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705816401 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1705816401 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_error.1821231304 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4249290197 ps |
| CPU time | 100.46 seconds |
| Started | Oct 03 02:54:06 AM UTC 24 |
| Finished | Oct 03 02:55:49 AM UTC 24 |
| Peak memory | 310508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821231304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1821231304 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.1061597890 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 531750539 ps |
| CPU time | 6.75 seconds |
| Started | Oct 03 02:55:10 AM UTC 24 |
| Finished | Oct 03 02:55:18 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061597890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1061597890 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.1169948023 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 138936410 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 02:55:19 AM UTC 24 |
| Finished | Oct 03 02:55:22 AM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169948023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1169948023 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2432103212 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 85039531943 ps |
| CPU time | 2110.32 seconds |
| Started | Oct 03 02:52:57 AM UTC 24 |
| Finished | Oct 03 03:28:35 AM UTC 24 |
| Peak memory | 2139224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432103212 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2432103212 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.757922067 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3348593064 ps |
| CPU time | 165.82 seconds |
| Started | Oct 03 02:53:31 AM UTC 24 |
| Finished | Oct 03 02:56:19 AM UTC 24 |
| Peak memory | 296212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757922067 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.757922067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.3648975591 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1780363138 ps |
| CPU time | 58.21 seconds |
| Started | Oct 03 02:52:35 AM UTC 24 |
| Finished | Oct 03 02:53:35 AM UTC 24 |
| Peak memory | 236428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648975591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3648975591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.2787159730 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 43502092273 ps |
| CPU time | 922.48 seconds |
| Started | Oct 03 02:55:23 AM UTC 24 |
| Finished | Oct 03 03:10:58 AM UTC 24 |
| Peak memory | 380220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787159730 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2787159730 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.2882377922 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 12965724 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 02:57:19 AM UTC 24 |
| Finished | Oct 03 02:57:21 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882377922 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2882377922 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_app.2251122938 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 9692015808 ps |
| CPU time | 323.81 seconds |
| Started | Oct 03 02:56:20 AM UTC 24 |
| Finished | Oct 03 03:01:49 AM UTC 24 |
| Peak memory | 461804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251122938 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2251122938 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.1421163983 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 28395048650 ps |
| CPU time | 1658.14 seconds |
| Started | Oct 03 02:56:18 AM UTC 24 |
| Finished | Oct 03 03:24:17 AM UTC 24 |
| Peak memory | 255020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421163983 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1421163983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.1754655794 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1845367110 ps |
| CPU time | 19.04 seconds |
| Started | Oct 03 02:56:41 AM UTC 24 |
| Finished | Oct 03 02:57:01 AM UTC 24 |
| Peak memory | 236652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754655794 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1754655794 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_error.1393743302 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 16168000098 ps |
| CPU time | 248.3 seconds |
| Started | Oct 03 02:56:57 AM UTC 24 |
| Finished | Oct 03 03:01:09 AM UTC 24 |
| Peak memory | 443428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393743302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1393743302 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.1801623492 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 54757036 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 02:57:14 AM UTC 24 |
| Finished | Oct 03 02:57:17 AM UTC 24 |
| Peak memory | 232016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801623492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1801623492 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.148739993 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 609368406985 ps |
| CPU time | 5942.4 seconds |
| Started | Oct 03 02:55:53 AM UTC 24 |
| Finished | Oct 03 04:36:06 AM UTC 24 |
| Peak memory | 4973904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148739993 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.148739993 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.3146606360 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 27029403344 ps |
| CPU time | 188.27 seconds |
| Started | Oct 03 02:56:11 AM UTC 24 |
| Finished | Oct 03 02:59:23 AM UTC 24 |
| Peak memory | 365612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146606360 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3146606360 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.1220649257 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1395184798 ps |
| CPU time | 18.46 seconds |
| Started | Oct 03 02:55:51 AM UTC 24 |
| Finished | Oct 03 02:56:11 AM UTC 24 |
| Peak memory | 236508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220649257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1220649257 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.1414522503 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 58606303494 ps |
| CPU time | 1101.54 seconds |
| Started | Oct 03 02:57:17 AM UTC 24 |
| Finished | Oct 03 03:15:51 AM UTC 24 |
| Peak memory | 400704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414522503 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1414522503 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.211244413 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 69932890 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 02:59:59 AM UTC 24 |
| Finished | Oct 03 03:00:01 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211244413 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.211244413 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_app.400992097 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 5531293509 ps |
| CPU time | 155.85 seconds |
| Started | Oct 03 02:58:56 AM UTC 24 |
| Finished | Oct 03 03:01:35 AM UTC 24 |
| Peak memory | 320536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400992097 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.400992097 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.2309226349 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 12629840760 ps |
| CPU time | 1250.4 seconds |
| Started | Oct 03 02:58:41 AM UTC 24 |
| Finished | Oct 03 03:19:47 AM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309226349 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2309226349 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1667334615 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4616889327 ps |
| CPU time | 44.42 seconds |
| Started | Oct 03 02:59:11 AM UTC 24 |
| Finished | Oct 03 02:59:57 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667334615 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1667334615 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_error.2495680747 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 19538984628 ps |
| CPU time | 433.05 seconds |
| Started | Oct 03 02:59:24 AM UTC 24 |
| Finished | Oct 03 03:06:43 AM UTC 24 |
| Peak memory | 367828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495680747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2495680747 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.3516425798 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 7009729299 ps |
| CPU time | 16.55 seconds |
| Started | Oct 03 02:59:49 AM UTC 24 |
| Finished | Oct 03 03:00:06 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516425798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3516425798 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.3938039553 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 67840996 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 02:59:56 AM UTC 24 |
| Finished | Oct 03 02:59:59 AM UTC 24 |
| Peak memory | 234076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938039553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3938039553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.677337832 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 17699019369 ps |
| CPU time | 643.13 seconds |
| Started | Oct 03 02:57:45 AM UTC 24 |
| Finished | Oct 03 03:08:38 AM UTC 24 |
| Peak memory | 814116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677337832 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.677337832 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.1456241818 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3839964032 ps |
| CPU time | 338.6 seconds |
| Started | Oct 03 02:58:01 AM UTC 24 |
| Finished | Oct 03 03:03:45 AM UTC 24 |
| Peak memory | 338924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456241818 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1456241818 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.2999120356 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1721233360 ps |
| CPU time | 36.67 seconds |
| Started | Oct 03 02:57:22 AM UTC 24 |
| Finished | Oct 03 02:58:00 AM UTC 24 |
| Peak memory | 236640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999120356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2999120356 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.793025337 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4031516427 ps |
| CPU time | 293.81 seconds |
| Started | Oct 03 02:59:58 AM UTC 24 |
| Finished | Oct 03 03:04:56 AM UTC 24 |
| Peak memory | 285792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793025337 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.793025337 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.3994865499 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 15775992 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 03:01:57 AM UTC 24 |
| Finished | Oct 03 03:01:59 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994865499 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3994865499 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_app.3866636548 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 5387673225 ps |
| CPU time | 281.96 seconds |
| Started | Oct 03 03:01:10 AM UTC 24 |
| Finished | Oct 03 03:05:57 AM UTC 24 |
| Peak memory | 328744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866636548 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3866636548 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.3402807530 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 57120545702 ps |
| CPU time | 1918.1 seconds |
| Started | Oct 03 03:00:28 AM UTC 24 |
| Finished | Oct 03 03:32:49 AM UTC 24 |
| Peak memory | 273444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402807530 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3402807530 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.2318231399 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 60020183651 ps |
| CPU time | 376.09 seconds |
| Started | Oct 03 03:01:20 AM UTC 24 |
| Finished | Oct 03 03:07:42 AM UTC 24 |
| Peak memory | 490588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318231399 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2318231399 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_error.210905577 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 7016084852 ps |
| CPU time | 196.66 seconds |
| Started | Oct 03 03:01:34 AM UTC 24 |
| Finished | Oct 03 03:04:54 AM UTC 24 |
| Peak memory | 334884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210905577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.210905577 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.2009708398 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 5765215560 ps |
| CPU time | 19.47 seconds |
| Started | Oct 03 03:01:36 AM UTC 24 |
| Finished | Oct 03 03:01:56 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009708398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2009708398 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.3526757286 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 226335888 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 03:01:50 AM UTC 24 |
| Finished | Oct 03 03:01:53 AM UTC 24 |
| Peak memory | 234080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526757286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3526757286 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.944048830 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 184463106466 ps |
| CPU time | 2196.25 seconds |
| Started | Oct 03 03:00:02 AM UTC 24 |
| Finished | Oct 03 03:37:09 AM UTC 24 |
| Peak memory | 1299800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944048830 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.944048830 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.979263217 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 91816549891 ps |
| CPU time | 616.24 seconds |
| Started | Oct 03 03:00:07 AM UTC 24 |
| Finished | Oct 03 03:10:32 AM UTC 24 |
| Peak memory | 634024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979263217 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.979263217 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.567365259 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2631358442 ps |
| CPU time | 86.62 seconds |
| Started | Oct 03 03:00:01 AM UTC 24 |
| Finished | Oct 03 03:01:33 AM UTC 24 |
| Peak memory | 236604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567365259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.567365259 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.822239108 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 305419371390 ps |
| CPU time | 1758.02 seconds |
| Started | Oct 03 03:01:54 AM UTC 24 |
| Finished | Oct 03 03:31:34 AM UTC 24 |
| Peak memory | 863616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822239108 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.822239108 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.2108659173 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 20734526 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 03:04:25 AM UTC 24 |
| Finished | Oct 03 03:04:27 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108659173 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2108659173 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_app.1895528286 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 10686988022 ps |
| CPU time | 364.35 seconds |
| Started | Oct 03 03:03:04 AM UTC 24 |
| Finished | Oct 03 03:09:14 AM UTC 24 |
| Peak memory | 347148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895528286 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1895528286 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.591866205 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 17808580448 ps |
| CPU time | 747.81 seconds |
| Started | Oct 03 03:03:00 AM UTC 24 |
| Finished | Oct 03 03:15:37 AM UTC 24 |
| Peak memory | 257000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591866205 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.591866205 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1588647438 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 6057998521 ps |
| CPU time | 290.27 seconds |
| Started | Oct 03 03:03:11 AM UTC 24 |
| Finished | Oct 03 03:08:06 AM UTC 24 |
| Peak memory | 326668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588647438 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1588647438 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_error.2343188995 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 11291539640 ps |
| CPU time | 86.5 seconds |
| Started | Oct 03 03:03:46 AM UTC 24 |
| Finished | Oct 03 03:05:15 AM UTC 24 |
| Peak memory | 302064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343188995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2343188995 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.3554845844 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2997775064 ps |
| CPU time | 14.94 seconds |
| Started | Oct 03 03:03:48 AM UTC 24 |
| Finished | Oct 03 03:04:05 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554845844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3554845844 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3523215923 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 50877445315 ps |
| CPU time | 1738.65 seconds |
| Started | Oct 03 03:02:46 AM UTC 24 |
| Finished | Oct 03 03:32:06 AM UTC 24 |
| Peak memory | 1997864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523215923 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3523215923 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.2929591369 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 21707620216 ps |
| CPU time | 340.38 seconds |
| Started | Oct 03 03:02:48 AM UTC 24 |
| Finished | Oct 03 03:08:34 AM UTC 24 |
| Peak memory | 451560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929591369 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2929591369 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.1095190994 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1766749598 ps |
| CPU time | 57.46 seconds |
| Started | Oct 03 03:02:00 AM UTC 24 |
| Finished | Oct 03 03:02:59 AM UTC 24 |
| Peak memory | 236476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095190994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1095190994 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.2837190267 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 72828812231 ps |
| CPU time | 985.37 seconds |
| Started | Oct 03 03:04:06 AM UTC 24 |
| Finished | Oct 03 03:20:43 AM UTC 24 |
| Peak memory | 349556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837190267 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2837190267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.155613336 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 94397653 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 03:06:44 AM UTC 24 |
| Finished | Oct 03 03:06:46 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155613336 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.155613336 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_app.2137949310 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 83652099103 ps |
| CPU time | 440.48 seconds |
| Started | Oct 03 03:05:21 AM UTC 24 |
| Finished | Oct 03 03:12:48 AM UTC 24 |
| Peak memory | 482348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137949310 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2137949310 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.2898414410 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 25077400821 ps |
| CPU time | 1066.06 seconds |
| Started | Oct 03 03:05:16 AM UTC 24 |
| Finished | Oct 03 03:23:15 AM UTC 24 |
| Peak memory | 265452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898414410 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2898414410 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.3001643928 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 32316384749 ps |
| CPU time | 270.84 seconds |
| Started | Oct 03 03:05:33 AM UTC 24 |
| Finished | Oct 03 03:10:08 AM UTC 24 |
| Peak memory | 386028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001643928 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3001643928 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_error.959499759 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 25320421143 ps |
| CPU time | 142.53 seconds |
| Started | Oct 03 03:05:58 AM UTC 24 |
| Finished | Oct 03 03:08:24 AM UTC 24 |
| Peak memory | 320684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959499759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.959499759 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.3195029907 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1207966593 ps |
| CPU time | 14.95 seconds |
| Started | Oct 03 03:05:58 AM UTC 24 |
| Finished | Oct 03 03:06:14 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195029907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3195029907 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.1993815772 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 36852599 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 03:06:15 AM UTC 24 |
| Finished | Oct 03 03:06:19 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993815772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1993815772 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.1304424656 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 83763779098 ps |
| CPU time | 2001.58 seconds |
| Started | Oct 03 03:04:55 AM UTC 24 |
| Finished | Oct 03 03:38:41 AM UTC 24 |
| Peak memory | 1053784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304424656 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.1304424656 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.410564397 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4336972065 ps |
| CPU time | 352.91 seconds |
| Started | Oct 03 03:04:57 AM UTC 24 |
| Finished | Oct 03 03:10:55 AM UTC 24 |
| Peak memory | 340964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410564397 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.410564397 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.3444628392 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 9380481684 ps |
| CPU time | 87.03 seconds |
| Started | Oct 03 03:04:28 AM UTC 24 |
| Finished | Oct 03 03:05:58 AM UTC 24 |
| Peak memory | 236824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444628392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3444628392 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.2852568067 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3934188832 ps |
| CPU time | 248.84 seconds |
| Started | Oct 03 03:06:21 AM UTC 24 |
| Finished | Oct 03 03:10:34 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852568067 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2852568067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.3696729370 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 16872923 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 03:08:46 AM UTC 24 |
| Finished | Oct 03 03:08:49 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696729370 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3696729370 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_app.225878831 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 20901921189 ps |
| CPU time | 393.71 seconds |
| Started | Oct 03 03:08:20 AM UTC 24 |
| Finished | Oct 03 03:14:59 AM UTC 24 |
| Peak memory | 482288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225878831 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.225878831 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.1731381092 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 6499700197 ps |
| CPU time | 624.55 seconds |
| Started | Oct 03 03:08:06 AM UTC 24 |
| Finished | Oct 03 03:18:40 AM UTC 24 |
| Peak memory | 244696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731381092 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.1731381092 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.3617587193 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 14351171964 ps |
| CPU time | 379.92 seconds |
| Started | Oct 03 03:08:25 AM UTC 24 |
| Finished | Oct 03 03:14:50 AM UTC 24 |
| Peak memory | 492588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617587193 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3617587193 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_error.3821232296 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 30353009985 ps |
| CPU time | 429.22 seconds |
| Started | Oct 03 03:08:35 AM UTC 24 |
| Finished | Oct 03 03:15:51 AM UTC 24 |
| Peak memory | 533548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821232296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3821232296 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.1048336369 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 993341048 ps |
| CPU time | 8.77 seconds |
| Started | Oct 03 03:08:36 AM UTC 24 |
| Finished | Oct 03 03:08:46 AM UTC 24 |
| Peak memory | 228624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048336369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1048336369 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.3410080933 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 116344183 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 03:08:38 AM UTC 24 |
| Finished | Oct 03 03:08:41 AM UTC 24 |
| Peak memory | 234576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410080933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3410080933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3305689640 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 62476155647 ps |
| CPU time | 2760.67 seconds |
| Started | Oct 03 03:06:58 AM UTC 24 |
| Finished | Oct 03 03:53:32 AM UTC 24 |
| Peak memory | 2927788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305689640 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3305689640 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.3475281229 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5785617837 ps |
| CPU time | 365 seconds |
| Started | Oct 03 03:07:43 AM UTC 24 |
| Finished | Oct 03 03:13:54 AM UTC 24 |
| Peak memory | 353312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475281229 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3475281229 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.412775143 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 5318280112 ps |
| CPU time | 88.69 seconds |
| Started | Oct 03 03:06:48 AM UTC 24 |
| Finished | Oct 03 03:08:19 AM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412775143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.412775143 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.1725168289 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 224394775 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 03:08:42 AM UTC 24 |
| Finished | Oct 03 03:08:47 AM UTC 24 |
| Peak memory | 230580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725168289 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1725168289 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.1028273232 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 46937263 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 03:10:56 AM UTC 24 |
| Finished | Oct 03 03:10:58 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028273232 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1028273232 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_app.3956155243 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 10810798895 ps |
| CPU time | 290.86 seconds |
| Started | Oct 03 03:09:59 AM UTC 24 |
| Finished | Oct 03 03:14:55 AM UTC 24 |
| Peak memory | 419036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956155243 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3956155243 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.3507713305 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 17514902020 ps |
| CPU time | 1608.06 seconds |
| Started | Oct 03 03:09:34 AM UTC 24 |
| Finished | Oct 03 03:36:43 AM UTC 24 |
| Peak memory | 257068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507713305 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3507713305 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.4072311715 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4320542349 ps |
| CPU time | 57.34 seconds |
| Started | Oct 03 03:10:09 AM UTC 24 |
| Finished | Oct 03 03:11:08 AM UTC 24 |
| Peak memory | 265272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072311715 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.4072311715 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_error.1029820970 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 24753811715 ps |
| CPU time | 369.45 seconds |
| Started | Oct 03 03:10:33 AM UTC 24 |
| Finished | Oct 03 03:16:47 AM UTC 24 |
| Peak memory | 539816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029820970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1029820970 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.3593146130 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1129310676 ps |
| CPU time | 7.29 seconds |
| Started | Oct 03 03:10:35 AM UTC 24 |
| Finished | Oct 03 03:10:43 AM UTC 24 |
| Peak memory | 228412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593146130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3593146130 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.4126458528 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 251052834 ps |
| CPU time | 7.08 seconds |
| Started | Oct 03 03:10:44 AM UTC 24 |
| Finished | Oct 03 03:10:52 AM UTC 24 |
| Peak memory | 242720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126458528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.4126458528 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.3548334277 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 110741716182 ps |
| CPU time | 3790.68 seconds |
| Started | Oct 03 03:08:50 AM UTC 24 |
| Finished | Oct 03 04:12:50 AM UTC 24 |
| Peak memory | 1887268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548334277 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.3548334277 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.761737876 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 19205266003 ps |
| CPU time | 132.49 seconds |
| Started | Oct 03 03:09:15 AM UTC 24 |
| Finished | Oct 03 03:11:30 AM UTC 24 |
| Peak memory | 331092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761737876 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.761737876 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.452042184 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1960401768 ps |
| CPU time | 43.93 seconds |
| Started | Oct 03 03:08:47 AM UTC 24 |
| Finished | Oct 03 03:09:33 AM UTC 24 |
| Peak memory | 236432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452042184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.452042184 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.1816129252 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 112205329641 ps |
| CPU time | 3334.66 seconds |
| Started | Oct 03 03:10:53 AM UTC 24 |
| Finished | Oct 03 04:07:08 AM UTC 24 |
| Peak memory | 1461244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816129252 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1816129252 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2547587777 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 14176202 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 03:12:17 AM UTC 24 |
| Finished | Oct 03 03:12:19 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547587777 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2547587777 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_app.1876917289 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 64394324668 ps |
| CPU time | 440.11 seconds |
| Started | Oct 03 03:11:35 AM UTC 24 |
| Finished | Oct 03 03:19:01 AM UTC 24 |
| Peak memory | 566504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876917289 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1876917289 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.3709495424 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 11071386289 ps |
| CPU time | 620.52 seconds |
| Started | Oct 03 03:11:31 AM UTC 24 |
| Finished | Oct 03 03:22:00 AM UTC 24 |
| Peak memory | 244720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709495424 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3709495424 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.4009165674 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1749952822 ps |
| CPU time | 37.1 seconds |
| Started | Oct 03 03:11:37 AM UTC 24 |
| Finished | Oct 03 03:12:16 AM UTC 24 |
| Peak memory | 236460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009165674 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.4009165674 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_error.375373316 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 48273303050 ps |
| CPU time | 473.55 seconds |
| Started | Oct 03 03:11:43 AM UTC 24 |
| Finished | Oct 03 03:19:44 AM UTC 24 |
| Peak memory | 398360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375373316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.375373316 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.3223733949 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 567368699 ps |
| CPU time | 10.62 seconds |
| Started | Oct 03 03:11:54 AM UTC 24 |
| Finished | Oct 03 03:12:06 AM UTC 24 |
| Peak memory | 228408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223733949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3223733949 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.832278348 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 79706752 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 03:12:07 AM UTC 24 |
| Finished | Oct 03 03:12:09 AM UTC 24 |
| Peak memory | 232040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832278348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.832278348 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.1437833777 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 15495975479 ps |
| CPU time | 438.91 seconds |
| Started | Oct 03 03:10:59 AM UTC 24 |
| Finished | Oct 03 03:18:25 AM UTC 24 |
| Peak memory | 463852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437833777 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.1437833777 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.3223239769 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 7599250438 ps |
| CPU time | 225.9 seconds |
| Started | Oct 03 03:11:10 AM UTC 24 |
| Finished | Oct 03 03:14:59 AM UTC 24 |
| Peak memory | 365612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223239769 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3223239769 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.1647044949 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1001789501 ps |
| CPU time | 52.46 seconds |
| Started | Oct 03 03:10:59 AM UTC 24 |
| Finished | Oct 03 03:11:54 AM UTC 24 |
| Peak memory | 236400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647044949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1647044949 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.1571124635 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 11350336039 ps |
| CPU time | 661.2 seconds |
| Started | Oct 03 03:12:10 AM UTC 24 |
| Finished | Oct 03 03:23:21 AM UTC 24 |
| Peak memory | 351548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571124635 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1571124635 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.331279706 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 18167835 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 03:15:08 AM UTC 24 |
| Finished | Oct 03 03:15:10 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331279706 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.331279706 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_app.2232232227 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 5746866375 ps |
| CPU time | 205.03 seconds |
| Started | Oct 03 03:14:10 AM UTC 24 |
| Finished | Oct 03 03:17:38 AM UTC 24 |
| Peak memory | 300060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232232227 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2232232227 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.2527921835 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 170180352405 ps |
| CPU time | 1632.58 seconds |
| Started | Oct 03 03:13:55 AM UTC 24 |
| Finished | Oct 03 03:41:27 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527921835 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2527921835 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.1451315114 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 5066501644 ps |
| CPU time | 105.22 seconds |
| Started | Oct 03 03:14:51 AM UTC 24 |
| Finished | Oct 03 03:16:38 AM UTC 24 |
| Peak memory | 308204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451315114 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1451315114 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_error.517617874 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 43147482300 ps |
| CPU time | 391.54 seconds |
| Started | Oct 03 03:14:56 AM UTC 24 |
| Finished | Oct 03 03:21:33 AM UTC 24 |
| Peak memory | 531692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517617874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.517617874 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.204473899 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1414231962 ps |
| CPU time | 17.56 seconds |
| Started | Oct 03 03:15:00 AM UTC 24 |
| Finished | Oct 03 03:15:19 AM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204473899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.204473899 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.3801780203 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 62988395 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 03:15:00 AM UTC 24 |
| Finished | Oct 03 03:15:04 AM UTC 24 |
| Peak memory | 232680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801780203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3801780203 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.3338907343 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 131503888369 ps |
| CPU time | 2941.69 seconds |
| Started | Oct 03 03:12:49 AM UTC 24 |
| Finished | Oct 03 04:02:21 AM UTC 24 |
| Peak memory | 3406892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338907343 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.3338907343 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.3161409114 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1040522900 ps |
| CPU time | 96.41 seconds |
| Started | Oct 03 03:13:28 AM UTC 24 |
| Finished | Oct 03 03:15:07 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161409114 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3161409114 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.4650215 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 10338509954 ps |
| CPU time | 106.55 seconds |
| Started | Oct 03 03:12:20 AM UTC 24 |
| Finished | Oct 03 03:14:09 AM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4650215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.4650215 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.2965380522 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 80004003002 ps |
| CPU time | 358.98 seconds |
| Started | Oct 03 03:15:05 AM UTC 24 |
| Finished | Oct 03 03:21:08 AM UTC 24 |
| Peak memory | 318608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965380522 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2965380522 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.1988383288 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 52553322 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 02:10:10 AM UTC 24 |
| Finished | Oct 03 02:10:12 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988383288 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1988383288 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_app.3120953587 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 919748438 ps |
| CPU time | 78.69 seconds |
| Started | Oct 03 02:08:31 AM UTC 24 |
| Finished | Oct 03 02:09:52 AM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120953587 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3120953587 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1385945891 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 7840841805 ps |
| CPU time | 162.3 seconds |
| Started | Oct 03 02:08:33 AM UTC 24 |
| Finished | Oct 03 02:11:18 AM UTC 24 |
| Peak memory | 345096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385945891 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1385945891 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.3726883275 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 38379085190 ps |
| CPU time | 776.93 seconds |
| Started | Oct 03 02:07:50 AM UTC 24 |
| Finished | Oct 03 02:20:57 AM UTC 24 |
| Peak memory | 261156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726883275 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3726883275 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2854247403 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 126803486 ps |
| CPU time | 8.72 seconds |
| Started | Oct 03 02:09:34 AM UTC 24 |
| Finished | Oct 03 02:09:44 AM UTC 24 |
| Peak memory | 234452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854247403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2854247403 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3632872844 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 70973687 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 02:09:45 AM UTC 24 |
| Finished | Oct 03 02:09:48 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632872844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3632872844 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2713164709 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2202913942 ps |
| CPU time | 35.44 seconds |
| Started | Oct 03 02:09:48 AM UTC 24 |
| Finished | Oct 03 02:10:25 AM UTC 24 |
| Peak memory | 236528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713164709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2713164709 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.2452649838 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11863457025 ps |
| CPU time | 96.62 seconds |
| Started | Oct 03 02:08:33 AM UTC 24 |
| Finished | Oct 03 02:10:12 AM UTC 24 |
| Peak memory | 265388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452649838 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2452649838 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_error.1828566603 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3917612038 ps |
| CPU time | 252.28 seconds |
| Started | Oct 03 02:09:27 AM UTC 24 |
| Finished | Oct 03 02:13:43 AM UTC 24 |
| Peak memory | 345100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828566603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1828566603 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.859696503 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5155616148 ps |
| CPU time | 19.72 seconds |
| Started | Oct 03 02:09:32 AM UTC 24 |
| Finished | Oct 03 02:09:53 AM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859696503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.859696503 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.1246823415 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 60815315 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 02:09:54 AM UTC 24 |
| Finished | Oct 03 02:09:57 AM UTC 24 |
| Peak memory | 232600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246823415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1246823415 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.673150750 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 216358606876 ps |
| CPU time | 1417.43 seconds |
| Started | Oct 03 02:07:37 AM UTC 24 |
| Finished | Oct 03 02:31:32 AM UTC 24 |
| Peak memory | 1750244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673150750 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.673150750 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.935328020 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3154403631 ps |
| CPU time | 178.15 seconds |
| Started | Oct 03 02:09:01 AM UTC 24 |
| Finished | Oct 03 02:12:02 AM UTC 24 |
| Peak memory | 290216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935328020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.935328020 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.3140375681 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 11458214496 ps |
| CPU time | 41.83 seconds |
| Started | Oct 03 02:10:02 AM UTC 24 |
| Finished | Oct 03 02:10:45 AM UTC 24 |
| Peak memory | 274456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140375681 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3140375681 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.2397189957 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 39237168583 ps |
| CPU time | 103.93 seconds |
| Started | Oct 03 02:07:40 AM UTC 24 |
| Finished | Oct 03 02:09:26 AM UTC 24 |
| Peak memory | 312352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397189957 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2397189957 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.3564189188 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 6521033309 ps |
| CPU time | 83.62 seconds |
| Started | Oct 03 02:07:34 AM UTC 24 |
| Finished | Oct 03 02:09:00 AM UTC 24 |
| Peak memory | 236584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564189188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3564189188 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.442319956 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 344412408 ps |
| CPU time | 4.11 seconds |
| Started | Oct 03 02:08:22 AM UTC 24 |
| Finished | Oct 03 02:08:27 AM UTC 24 |
| Peak memory | 236476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442319956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.442319956 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2195041191 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 312725745 ps |
| CPU time | 3.52 seconds |
| Started | Oct 03 02:08:28 AM UTC 24 |
| Finished | Oct 03 02:08:33 AM UTC 24 |
| Peak memory | 236404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195041191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2195041191 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.3278262404 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 63040409966 ps |
| CPU time | 2702.44 seconds |
| Started | Oct 03 02:07:54 AM UTC 24 |
| Finished | Oct 03 02:53:30 AM UTC 24 |
| Peak memory | 3109856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278262404 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.3278262404 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.1012339173 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 429554908147 ps |
| CPU time | 3110.24 seconds |
| Started | Oct 03 02:08:01 AM UTC 24 |
| Finished | Oct 03 03:00:27 AM UTC 24 |
| Peak memory | 2970620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012339173 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1012339173 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3960529243 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1397745348 ps |
| CPU time | 27.39 seconds |
| Started | Oct 03 02:08:04 AM UTC 24 |
| Finished | Oct 03 02:08:32 AM UTC 24 |
| Peak memory | 236340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960529243 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3960529243 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.1225275489 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 33165277465 ps |
| CPU time | 1556.92 seconds |
| Started | Oct 03 02:08:05 AM UTC 24 |
| Finished | Oct 03 02:34:20 AM UTC 24 |
| Peak memory | 1700768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225275489 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1225275489 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1499376107 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 21711340145 ps |
| CPU time | 2853.57 seconds |
| Started | Oct 03 02:08:10 AM UTC 24 |
| Finished | Oct 03 02:56:18 AM UTC 24 |
| Peak memory | 1366928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499376107 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1499376107 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.4104776519 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 156391034405 ps |
| CPU time | 1920.77 seconds |
| Started | Oct 03 02:08:21 AM UTC 24 |
| Finished | Oct 03 02:40:43 AM UTC 24 |
| Peak memory | 1139604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104776519 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.4104776519 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.1028251546 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 49423664 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 03:17:01 AM UTC 24 |
| Finished | Oct 03 03:17:04 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028251546 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1028251546 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_app.1313133855 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 48040344946 ps |
| CPU time | 407.89 seconds |
| Started | Oct 03 03:15:52 AM UTC 24 |
| Finished | Oct 03 03:22:46 AM UTC 24 |
| Peak memory | 472156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313133855 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1313133855 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.2226250433 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 86460688501 ps |
| CPU time | 484.17 seconds |
| Started | Oct 03 03:15:51 AM UTC 24 |
| Finished | Oct 03 03:24:02 AM UTC 24 |
| Peak memory | 252972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226250433 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2226250433 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.4217160976 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4132026603 ps |
| CPU time | 139.05 seconds |
| Started | Oct 03 03:16:40 AM UTC 24 |
| Finished | Oct 03 03:19:01 AM UTC 24 |
| Peak memory | 277540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217160976 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.4217160976 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_error.571549653 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 11462605206 ps |
| CPU time | 219.66 seconds |
| Started | Oct 03 03:16:48 AM UTC 24 |
| Finished | Oct 03 03:20:31 AM UTC 24 |
| Peak memory | 312360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571549653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.571549653 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.608646909 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 11584431130 ps |
| CPU time | 10.39 seconds |
| Started | Oct 03 03:16:49 AM UTC 24 |
| Finished | Oct 03 03:17:00 AM UTC 24 |
| Peak memory | 228664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608646909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.608646909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.3568996997 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 73670568 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 03:16:50 AM UTC 24 |
| Finished | Oct 03 03:16:53 AM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568996997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.3568996997 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.1195240576 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 9063811879 ps |
| CPU time | 767.3 seconds |
| Started | Oct 03 03:15:20 AM UTC 24 |
| Finished | Oct 03 03:28:17 AM UTC 24 |
| Peak memory | 678940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195240576 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.1195240576 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.4233026896 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 53821979116 ps |
| CPU time | 426.82 seconds |
| Started | Oct 03 03:15:38 AM UTC 24 |
| Finished | Oct 03 03:22:51 AM UTC 24 |
| Peak memory | 574696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233026896 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.4233026896 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.681872436 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 18565409797 ps |
| CPU time | 94.88 seconds |
| Started | Oct 03 03:15:11 AM UTC 24 |
| Finished | Oct 03 03:16:48 AM UTC 24 |
| Peak memory | 236556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681872436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.681872436 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.401630699 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 26337223363 ps |
| CPU time | 862.34 seconds |
| Started | Oct 03 03:16:54 AM UTC 24 |
| Finished | Oct 03 03:31:29 AM UTC 24 |
| Peak memory | 411036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401630699 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.401630699 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.399274280 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 40396307 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 03:19:06 AM UTC 24 |
| Finished | Oct 03 03:19:08 AM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399274280 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.399274280 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_app.799519559 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2924278092 ps |
| CPU time | 27.15 seconds |
| Started | Oct 03 03:18:34 AM UTC 24 |
| Finished | Oct 03 03:19:03 AM UTC 24 |
| Peak memory | 263220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799519559 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.799519559 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.1910338791 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 41005007293 ps |
| CPU time | 449.17 seconds |
| Started | Oct 03 03:18:25 AM UTC 24 |
| Finished | Oct 03 03:26:01 AM UTC 24 |
| Peak memory | 253160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910338791 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1910338791 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.3977880368 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 10675076570 ps |
| CPU time | 312.77 seconds |
| Started | Oct 03 03:18:40 AM UTC 24 |
| Finished | Oct 03 03:23:58 AM UTC 24 |
| Peak memory | 330992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977880368 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3977880368 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_error.3031519024 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 24974220738 ps |
| CPU time | 336.01 seconds |
| Started | Oct 03 03:19:02 AM UTC 24 |
| Finished | Oct 03 03:24:43 AM UTC 24 |
| Peak memory | 400668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031519024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3031519024 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.3280741705 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1107173197 ps |
| CPU time | 12.87 seconds |
| Started | Oct 03 03:19:03 AM UTC 24 |
| Finished | Oct 03 03:19:17 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280741705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3280741705 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.3406295598 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 41589458 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 03:19:03 AM UTC 24 |
| Finished | Oct 03 03:19:06 AM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406295598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3406295598 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.33599278 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 313848004438 ps |
| CPU time | 1958.22 seconds |
| Started | Oct 03 03:17:39 AM UTC 24 |
| Finished | Oct 03 03:50:42 AM UTC 24 |
| Peak memory | 1178788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33599278 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.33599278 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.1343931796 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 963104922 ps |
| CPU time | 27.51 seconds |
| Started | Oct 03 03:18:05 AM UTC 24 |
| Finished | Oct 03 03:18:34 AM UTC 24 |
| Peak memory | 236696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343931796 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1343931796 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.2123711024 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 38625512921 ps |
| CPU time | 113.59 seconds |
| Started | Oct 03 03:17:04 AM UTC 24 |
| Finished | Oct 03 03:19:00 AM UTC 24 |
| Peak memory | 236528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123711024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2123711024 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.1856352207 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 15450535112 ps |
| CPU time | 563.75 seconds |
| Started | Oct 03 03:19:04 AM UTC 24 |
| Finished | Oct 03 03:28:36 AM UTC 24 |
| Peak memory | 531888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856352207 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1856352207 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.2398237016 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 75148775 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 03:21:36 AM UTC 24 |
| Finished | Oct 03 03:21:38 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398237016 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2398237016 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_app.3079299121 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 82701896379 ps |
| CPU time | 349.41 seconds |
| Started | Oct 03 03:20:32 AM UTC 24 |
| Finished | Oct 03 03:26:27 AM UTC 24 |
| Peak memory | 465896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079299121 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3079299121 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.2096611497 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 30478740659 ps |
| CPU time | 900.28 seconds |
| Started | Oct 03 03:19:48 AM UTC 24 |
| Finished | Oct 03 03:34:59 AM UTC 24 |
| Peak memory | 257052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096611497 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2096611497 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.592711498 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3548949404 ps |
| CPU time | 189.6 seconds |
| Started | Oct 03 03:20:44 AM UTC 24 |
| Finished | Oct 03 03:23:57 AM UTC 24 |
| Peak memory | 271596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592711498 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.592711498 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_error.1063205459 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1210338291 ps |
| CPU time | 51.93 seconds |
| Started | Oct 03 03:21:02 AM UTC 24 |
| Finished | Oct 03 03:21:56 AM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063205459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1063205459 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.3064511770 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2903270586 ps |
| CPU time | 20.16 seconds |
| Started | Oct 03 03:21:09 AM UTC 24 |
| Finished | Oct 03 03:21:31 AM UTC 24 |
| Peak memory | 228492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064511770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3064511770 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.1441649677 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 44833280 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 03:21:32 AM UTC 24 |
| Finished | Oct 03 03:21:35 AM UTC 24 |
| Peak memory | 234472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441649677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1441649677 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.4211764171 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 27384990203 ps |
| CPU time | 3319.36 seconds |
| Started | Oct 03 03:19:17 AM UTC 24 |
| Finished | Oct 03 04:15:19 AM UTC 24 |
| Peak memory | 1864744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211764171 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.4211764171 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.2717103167 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 30514256666 ps |
| CPU time | 554.34 seconds |
| Started | Oct 03 03:19:45 AM UTC 24 |
| Finished | Oct 03 03:29:07 AM UTC 24 |
| Peak memory | 590880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717103167 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2717103167 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.877402763 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 9113177355 ps |
| CPU time | 109.51 seconds |
| Started | Oct 03 03:19:09 AM UTC 24 |
| Finished | Oct 03 03:21:01 AM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877402763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.877402763 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.510072126 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 145022274577 ps |
| CPU time | 1206.68 seconds |
| Started | Oct 03 03:21:34 AM UTC 24 |
| Finished | Oct 03 03:41:56 AM UTC 24 |
| Peak memory | 779576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510072126 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.510072126 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.393702836 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 20386737 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 03:23:17 AM UTC 24 |
| Finished | Oct 03 03:23:19 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393702836 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.393702836 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_app.112384978 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 14714655014 ps |
| CPU time | 221.4 seconds |
| Started | Oct 03 03:22:21 AM UTC 24 |
| Finished | Oct 03 03:26:06 AM UTC 24 |
| Peak memory | 300000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112384978 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.112384978 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.492360453 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 5116700986 ps |
| CPU time | 239.15 seconds |
| Started | Oct 03 03:22:00 AM UTC 24 |
| Finished | Oct 03 03:26:03 AM UTC 24 |
| Peak memory | 238676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492360453 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.492360453 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3004312338 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 10808458918 ps |
| CPU time | 268.44 seconds |
| Started | Oct 03 03:22:22 AM UTC 24 |
| Finished | Oct 03 03:26:55 AM UTC 24 |
| Peak memory | 379996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004312338 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3004312338 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_error.1431005378 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2856086758 ps |
| CPU time | 109.85 seconds |
| Started | Oct 03 03:22:48 AM UTC 24 |
| Finished | Oct 03 03:24:41 AM UTC 24 |
| Peak memory | 312356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431005378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1431005378 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.3880173456 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 5806445530 ps |
| CPU time | 17.92 seconds |
| Started | Oct 03 03:22:51 AM UTC 24 |
| Finished | Oct 03 03:23:11 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880173456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3880173456 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.380390492 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 64944843 ps |
| CPU time | 2.66 seconds |
| Started | Oct 03 03:23:11 AM UTC 24 |
| Finished | Oct 03 03:23:15 AM UTC 24 |
| Peak memory | 234540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380390492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.380390492 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.2092451410 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 51179169597 ps |
| CPU time | 3105.09 seconds |
| Started | Oct 03 03:21:57 AM UTC 24 |
| Finished | Oct 03 04:14:20 AM UTC 24 |
| Peak memory | 1748112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092451410 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.2092451410 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.1668644252 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 18924153479 ps |
| CPU time | 455 seconds |
| Started | Oct 03 03:21:57 AM UTC 24 |
| Finished | Oct 03 03:29:38 AM UTC 24 |
| Peak memory | 527328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668644252 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1668644252 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.167786651 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 995559047 ps |
| CPU time | 15.84 seconds |
| Started | Oct 03 03:21:39 AM UTC 24 |
| Finished | Oct 03 03:21:56 AM UTC 24 |
| Peak memory | 236392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167786651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.167786651 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.2062596648 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 21322441305 ps |
| CPU time | 1753.66 seconds |
| Started | Oct 03 03:23:15 AM UTC 24 |
| Finished | Oct 03 03:52:51 AM UTC 24 |
| Peak memory | 476588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062596648 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2062596648 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.2933007403 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 22973567 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 03:24:53 AM UTC 24 |
| Finished | Oct 03 03:24:55 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933007403 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2933007403 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_app.100669923 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 11979982733 ps |
| CPU time | 430.63 seconds |
| Started | Oct 03 03:24:04 AM UTC 24 |
| Finished | Oct 03 03:31:21 AM UTC 24 |
| Peak memory | 521244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100669923 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.100669923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.4012529639 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5856392406 ps |
| CPU time | 78.63 seconds |
| Started | Oct 03 03:24:00 AM UTC 24 |
| Finished | Oct 03 03:25:20 AM UTC 24 |
| Peak memory | 247084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012529639 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.4012529639 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.1823817666 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 15888277584 ps |
| CPU time | 163.8 seconds |
| Started | Oct 03 03:24:18 AM UTC 24 |
| Finished | Oct 03 03:27:05 AM UTC 24 |
| Peak memory | 334832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823817666 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1823817666 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_error.398511536 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 43324289790 ps |
| CPU time | 356.57 seconds |
| Started | Oct 03 03:24:24 AM UTC 24 |
| Finished | Oct 03 03:30:26 AM UTC 24 |
| Peak memory | 496656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398511536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.398511536 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.2766713638 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 877599222 ps |
| CPU time | 10.48 seconds |
| Started | Oct 03 03:24:41 AM UTC 24 |
| Finished | Oct 03 03:24:53 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766713638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2766713638 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.1096868756 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 70626520 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 03:24:44 AM UTC 24 |
| Finished | Oct 03 03:24:48 AM UTC 24 |
| Peak memory | 234524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096868756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1096868756 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.1666081024 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 90870898437 ps |
| CPU time | 2849.57 seconds |
| Started | Oct 03 03:23:22 AM UTC 24 |
| Finished | Oct 03 04:11:28 AM UTC 24 |
| Peak memory | 1524824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666081024 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.1666081024 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.294988109 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 205368327242 ps |
| CPU time | 354.36 seconds |
| Started | Oct 03 03:24:00 AM UTC 24 |
| Finished | Oct 03 03:29:59 AM UTC 24 |
| Peak memory | 506964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294988109 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.294988109 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.4106909048 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2255561475 ps |
| CPU time | 90.27 seconds |
| Started | Oct 03 03:23:20 AM UTC 24 |
| Finished | Oct 03 03:24:52 AM UTC 24 |
| Peak memory | 236516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106909048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.4106909048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.952061391 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 23280981392 ps |
| CPU time | 817.96 seconds |
| Started | Oct 03 03:24:49 AM UTC 24 |
| Finished | Oct 03 03:38:37 AM UTC 24 |
| Peak memory | 910656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952061391 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.952061391 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.3669959889 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 15329162 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 03:26:27 AM UTC 24 |
| Finished | Oct 03 03:26:30 AM UTC 24 |
| Peak memory | 226888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669959889 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3669959889 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_app.2292142613 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 9648733948 ps |
| CPU time | 128.26 seconds |
| Started | Oct 03 03:25:57 AM UTC 24 |
| Finished | Oct 03 03:28:07 AM UTC 24 |
| Peak memory | 308304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292142613 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2292142613 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.843140268 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 17661928400 ps |
| CPU time | 554.63 seconds |
| Started | Oct 03 03:25:47 AM UTC 24 |
| Finished | Oct 03 03:35:09 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843140268 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.843140268 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.1997478560 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 122102452217 ps |
| CPU time | 202.78 seconds |
| Started | Oct 03 03:26:02 AM UTC 24 |
| Finished | Oct 03 03:29:28 AM UTC 24 |
| Peak memory | 367916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997478560 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1997478560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_error.1573452827 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 11532354652 ps |
| CPU time | 460.19 seconds |
| Started | Oct 03 03:26:04 AM UTC 24 |
| Finished | Oct 03 03:33:51 AM UTC 24 |
| Peak memory | 490480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573452827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1573452827 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.1855758674 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2072527920 ps |
| CPU time | 7.3 seconds |
| Started | Oct 03 03:26:07 AM UTC 24 |
| Finished | Oct 03 03:26:16 AM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855758674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1855758674 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.1284952545 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 62552563 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 03:26:17 AM UTC 24 |
| Finished | Oct 03 03:26:20 AM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284952545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1284952545 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.4032374987 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 3018955396 ps |
| CPU time | 229.7 seconds |
| Started | Oct 03 03:24:56 AM UTC 24 |
| Finished | Oct 03 03:28:49 AM UTC 24 |
| Peak memory | 392168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032374987 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.4032374987 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.3263172674 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 30570209574 ps |
| CPU time | 599.85 seconds |
| Started | Oct 03 03:25:21 AM UTC 24 |
| Finished | Oct 03 03:35:29 AM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263172674 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3263172674 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.3822776490 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 8700313309 ps |
| CPU time | 50.84 seconds |
| Started | Oct 03 03:24:54 AM UTC 24 |
| Finished | Oct 03 03:25:46 AM UTC 24 |
| Peak memory | 236520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822776490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3822776490 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.691876923 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 63443229937 ps |
| CPU time | 945.58 seconds |
| Started | Oct 03 03:26:21 AM UTC 24 |
| Finished | Oct 03 03:42:18 AM UTC 24 |
| Peak memory | 1359144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691876923 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.691876923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.1017379260 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 49604260 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 03:28:46 AM UTC 24 |
| Finished | Oct 03 03:28:48 AM UTC 24 |
| Peak memory | 226648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017379260 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1017379260 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_app.3351480099 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1621046975 ps |
| CPU time | 52.86 seconds |
| Started | Oct 03 03:27:50 AM UTC 24 |
| Finished | Oct 03 03:28:45 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351480099 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3351480099 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.2688786905 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 28499653105 ps |
| CPU time | 1516.1 seconds |
| Started | Oct 03 03:27:29 AM UTC 24 |
| Finished | Oct 03 03:53:03 AM UTC 24 |
| Peak memory | 273448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688786905 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2688786905 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.4231802523 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 12208455944 ps |
| CPU time | 183.38 seconds |
| Started | Oct 03 03:28:09 AM UTC 24 |
| Finished | Oct 03 03:31:16 AM UTC 24 |
| Peak memory | 281684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231802523 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.4231802523 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_error.3315686850 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 85788293170 ps |
| CPU time | 539.08 seconds |
| Started | Oct 03 03:28:18 AM UTC 24 |
| Finished | Oct 03 03:37:24 AM UTC 24 |
| Peak memory | 676908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315686850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3315686850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.1314521295 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 17047867660 ps |
| CPU time | 19.57 seconds |
| Started | Oct 03 03:28:36 AM UTC 24 |
| Finished | Oct 03 03:28:57 AM UTC 24 |
| Peak memory | 230672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314521295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1314521295 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.205270431 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 53317790 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 03:28:37 AM UTC 24 |
| Finished | Oct 03 03:28:40 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205270431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.205270431 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.312050510 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 250643587837 ps |
| CPU time | 2619.35 seconds |
| Started | Oct 03 03:26:56 AM UTC 24 |
| Finished | Oct 03 04:11:07 AM UTC 24 |
| Peak memory | 1600552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312050510 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.312050510 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.888514018 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 183194621 ps |
| CPU time | 21.19 seconds |
| Started | Oct 03 03:27:06 AM UTC 24 |
| Finished | Oct 03 03:27:28 AM UTC 24 |
| Peak memory | 250728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888514018 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.888514018 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.751485699 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 3415399980 ps |
| CPU time | 76.78 seconds |
| Started | Oct 03 03:26:31 AM UTC 24 |
| Finished | Oct 03 03:27:50 AM UTC 24 |
| Peak memory | 236564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751485699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.751485699 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.1107037239 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 40576641045 ps |
| CPU time | 1669.53 seconds |
| Started | Oct 03 03:28:41 AM UTC 24 |
| Finished | Oct 03 03:56:52 AM UTC 24 |
| Peak memory | 773216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107037239 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1107037239 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.1999820827 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 45265522 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 03:30:03 AM UTC 24 |
| Finished | Oct 03 03:30:05 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999820827 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1999820827 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_app.1714016211 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 5760889951 ps |
| CPU time | 221.38 seconds |
| Started | Oct 03 03:29:08 AM UTC 24 |
| Finished | Oct 03 03:32:53 AM UTC 24 |
| Peak memory | 318676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714016211 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1714016211 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.4019582484 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 24230558163 ps |
| CPU time | 398.75 seconds |
| Started | Oct 03 03:28:58 AM UTC 24 |
| Finished | Oct 03 03:35:42 AM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019582484 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.4019582484 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.1456011703 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 26841822152 ps |
| CPU time | 269.2 seconds |
| Started | Oct 03 03:29:29 AM UTC 24 |
| Finished | Oct 03 03:34:02 AM UTC 24 |
| Peak memory | 326732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456011703 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1456011703 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_error.1280736669 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 17968446447 ps |
| CPU time | 146.69 seconds |
| Started | Oct 03 03:29:31 AM UTC 24 |
| Finished | Oct 03 03:32:01 AM UTC 24 |
| Peak memory | 359468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280736669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1280736669 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.802609746 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1154811748 ps |
| CPU time | 16.99 seconds |
| Started | Oct 03 03:29:39 AM UTC 24 |
| Finished | Oct 03 03:29:58 AM UTC 24 |
| Peak memory | 228412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802609746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.802609746 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.3248869158 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 35050892 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 03:29:59 AM UTC 24 |
| Finished | Oct 03 03:30:02 AM UTC 24 |
| Peak memory | 234472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248869158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3248869158 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.4257754467 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 30021270359 ps |
| CPU time | 1699.92 seconds |
| Started | Oct 03 03:28:50 AM UTC 24 |
| Finished | Oct 03 03:57:33 AM UTC 24 |
| Peak memory | 1070032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257754467 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.4257754467 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.889212888 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 19617584316 ps |
| CPU time | 324.59 seconds |
| Started | Oct 03 03:28:56 AM UTC 24 |
| Finished | Oct 03 03:34:25 AM UTC 24 |
| Peak memory | 335124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889212888 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.889212888 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.3027327327 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 12993157043 ps |
| CPU time | 84.09 seconds |
| Started | Oct 03 03:28:49 AM UTC 24 |
| Finished | Oct 03 03:30:15 AM UTC 24 |
| Peak memory | 236588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027327327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3027327327 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.3220851846 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 55723955722 ps |
| CPU time | 1002.54 seconds |
| Started | Oct 03 03:30:00 AM UTC 24 |
| Finished | Oct 03 03:46:55 AM UTC 24 |
| Peak memory | 679284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220851846 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3220851846 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.739257922 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 39346915 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 03:31:49 AM UTC 24 |
| Finished | Oct 03 03:31:51 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739257922 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.739257922 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_app.3888797305 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1126669655 ps |
| CPU time | 9.67 seconds |
| Started | Oct 03 03:31:16 AM UTC 24 |
| Finished | Oct 03 03:31:27 AM UTC 24 |
| Peak memory | 234588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888797305 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3888797305 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.2640970667 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 12178845892 ps |
| CPU time | 530.03 seconds |
| Started | Oct 03 03:31:09 AM UTC 24 |
| Finished | Oct 03 03:40:07 AM UTC 24 |
| Peak memory | 252912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640970667 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2640970667 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.1003523940 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 22597773449 ps |
| CPU time | 368.66 seconds |
| Started | Oct 03 03:31:16 AM UTC 24 |
| Finished | Oct 03 03:37:30 AM UTC 24 |
| Peak memory | 474448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003523940 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1003523940 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_error.3329564826 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2048719261 ps |
| CPU time | 102.76 seconds |
| Started | Oct 03 03:31:22 AM UTC 24 |
| Finished | Oct 03 03:33:08 AM UTC 24 |
| Peak memory | 269228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329564826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3329564826 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.780277859 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2081120930 ps |
| CPU time | 17.58 seconds |
| Started | Oct 03 03:31:29 AM UTC 24 |
| Finished | Oct 03 03:31:48 AM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780277859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.780277859 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.2818515888 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 708070240 ps |
| CPU time | 54.73 seconds |
| Started | Oct 03 03:31:30 AM UTC 24 |
| Finished | Oct 03 03:32:26 AM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818515888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2818515888 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.231138182 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 91794529684 ps |
| CPU time | 2494.07 seconds |
| Started | Oct 03 03:30:16 AM UTC 24 |
| Finished | Oct 03 04:12:21 AM UTC 24 |
| Peak memory | 1551504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231138182 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.231138182 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.29986473 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 544494771 ps |
| CPU time | 40.1 seconds |
| Started | Oct 03 03:30:26 AM UTC 24 |
| Finished | Oct 03 03:31:08 AM UTC 24 |
| Peak memory | 242532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29986473 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.29986473 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.3910450163 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4663773602 ps |
| CPU time | 67.28 seconds |
| Started | Oct 03 03:30:06 AM UTC 24 |
| Finished | Oct 03 03:31:15 AM UTC 24 |
| Peak memory | 236504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910450163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3910450163 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.207247877 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 264950411402 ps |
| CPU time | 2790.39 seconds |
| Started | Oct 03 03:31:35 AM UTC 24 |
| Finished | Oct 03 04:18:40 AM UTC 24 |
| Peak memory | 1471864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207247877 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.207247877 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.311913530 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 13596735 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 03:33:52 AM UTC 24 |
| Finished | Oct 03 03:33:54 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311913530 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.311913530 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_app.2659961275 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 8302702272 ps |
| CPU time | 191.18 seconds |
| Started | Oct 03 03:32:27 AM UTC 24 |
| Finished | Oct 03 03:35:41 AM UTC 24 |
| Peak memory | 281636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659961275 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2659961275 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.688153860 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 8703764702 ps |
| CPU time | 407.45 seconds |
| Started | Oct 03 03:32:08 AM UTC 24 |
| Finished | Oct 03 03:39:01 AM UTC 24 |
| Peak memory | 246748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688153860 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.688153860 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.1149153435 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1726667195 ps |
| CPU time | 84.84 seconds |
| Started | Oct 03 03:32:50 AM UTC 24 |
| Finished | Oct 03 03:34:17 AM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149153435 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1149153435 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_error.1125596444 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 9659301563 ps |
| CPU time | 309.42 seconds |
| Started | Oct 03 03:32:54 AM UTC 24 |
| Finished | Oct 03 03:38:09 AM UTC 24 |
| Peak memory | 447532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125596444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1125596444 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.1231414960 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 737929479 ps |
| CPU time | 10.29 seconds |
| Started | Oct 03 03:33:08 AM UTC 24 |
| Finished | Oct 03 03:33:20 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231414960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1231414960 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.3932395023 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 202324710 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 03:33:21 AM UTC 24 |
| Finished | Oct 03 03:33:24 AM UTC 24 |
| Peak memory | 234496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932395023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3932395023 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.1710192669 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 109333129042 ps |
| CPU time | 2564.57 seconds |
| Started | Oct 03 03:32:01 AM UTC 24 |
| Finished | Oct 03 04:15:18 AM UTC 24 |
| Peak memory | 2698280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710192669 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.1710192669 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.3919117226 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 8977838366 ps |
| CPU time | 330.85 seconds |
| Started | Oct 03 03:32:04 AM UTC 24 |
| Finished | Oct 03 03:37:39 AM UTC 24 |
| Peak memory | 439300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919117226 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3919117226 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.1026380038 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 166573361 ps |
| CPU time | 9.56 seconds |
| Started | Oct 03 03:31:52 AM UTC 24 |
| Finished | Oct 03 03:32:03 AM UTC 24 |
| Peak memory | 236400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026380038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1026380038 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.312369495 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 78379160400 ps |
| CPU time | 1055.66 seconds |
| Started | Oct 03 03:33:25 AM UTC 24 |
| Finished | Oct 03 03:51:14 AM UTC 24 |
| Peak memory | 1189180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312369495 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.312369495 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.293028242 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 55226170 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 02:12:47 AM UTC 24 |
| Finished | Oct 03 02:12:49 AM UTC 24 |
| Peak memory | 226652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293028242 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.293028242 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_app.3822531270 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3583421367 ps |
| CPU time | 57.2 seconds |
| Started | Oct 03 02:11:11 AM UTC 24 |
| Finished | Oct 03 02:12:10 AM UTC 24 |
| Peak memory | 244976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822531270 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3822531270 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2496019023 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 156080749 ps |
| CPU time | 12.5 seconds |
| Started | Oct 03 02:11:13 AM UTC 24 |
| Finished | Oct 03 02:11:27 AM UTC 24 |
| Peak memory | 244928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496019023 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2496019023 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.1073697076 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 93114751016 ps |
| CPU time | 1220.26 seconds |
| Started | Oct 03 02:10:18 AM UTC 24 |
| Finished | Oct 03 02:30:53 AM UTC 24 |
| Peak memory | 267296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073697076 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1073697076 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3507636237 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 771541506 ps |
| CPU time | 55.79 seconds |
| Started | Oct 03 02:11:49 AM UTC 24 |
| Finished | Oct 03 02:12:46 AM UTC 24 |
| Peak memory | 236124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507636237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3507636237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.4006761287 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 20803449 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 02:12:03 AM UTC 24 |
| Finished | Oct 03 02:12:05 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006761287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.4006761287 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.1541405173 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 253992873 ps |
| CPU time | 4.98 seconds |
| Started | Oct 03 02:12:06 AM UTC 24 |
| Finished | Oct 03 02:12:12 AM UTC 24 |
| Peak memory | 232648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541405173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1541405173 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.3517272508 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1003714009 ps |
| CPU time | 14.01 seconds |
| Started | Oct 03 02:11:33 AM UTC 24 |
| Finished | Oct 03 02:11:48 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517272508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3517272508 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.3567757790 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 58934372529 ps |
| CPU time | 1752.34 seconds |
| Started | Oct 03 02:10:14 AM UTC 24 |
| Finished | Oct 03 02:39:48 AM UTC 24 |
| Peak memory | 1115164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567757790 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.3567757790 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.2277216704 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 5047230536 ps |
| CPU time | 343.04 seconds |
| Started | Oct 03 02:11:19 AM UTC 24 |
| Finished | Oct 03 02:17:07 AM UTC 24 |
| Peak memory | 355604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277216704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2277216704 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.4235160322 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4551412705 ps |
| CPU time | 100.78 seconds |
| Started | Oct 03 02:12:13 AM UTC 24 |
| Finished | Oct 03 02:13:57 AM UTC 24 |
| Peak memory | 295028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235160322 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.4235160322 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.2193278332 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2723476687 ps |
| CPU time | 191.18 seconds |
| Started | Oct 03 02:10:18 AM UTC 24 |
| Finished | Oct 03 02:13:33 AM UTC 24 |
| Peak memory | 310556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193278332 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2193278332 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.3572647006 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 6617235628 ps |
| CPU time | 44.29 seconds |
| Started | Oct 03 02:10:14 AM UTC 24 |
| Finished | Oct 03 02:11:00 AM UTC 24 |
| Peak memory | 236524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572647006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3572647006 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.917207044 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 37728406653 ps |
| CPU time | 1035.64 seconds |
| Started | Oct 03 02:12:11 AM UTC 24 |
| Finished | Oct 03 02:29:40 AM UTC 24 |
| Peak memory | 333324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917207044 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.917207044 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all_with_rand_reset.3145606443 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3156518914 ps |
| CPU time | 76.39 seconds |
| Started | Oct 03 02:12:13 AM UTC 24 |
| Finished | Oct 03 02:13:32 AM UTC 24 |
| Peak memory | 263364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3145606443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_r and_reset.3145606443 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.167055445 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 226976155 ps |
| CPU time | 3.67 seconds |
| Started | Oct 03 02:11:06 AM UTC 24 |
| Finished | Oct 03 02:11:11 AM UTC 24 |
| Peak memory | 236604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167055445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.167055445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.245214634 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 283160133 ps |
| CPU time | 2.89 seconds |
| Started | Oct 03 02:11:10 AM UTC 24 |
| Finished | Oct 03 02:11:14 AM UTC 24 |
| Peak memory | 236528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245214634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.245214634 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.1879811048 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 163011216449 ps |
| CPU time | 3448.09 seconds |
| Started | Oct 03 02:10:26 AM UTC 24 |
| Finished | Oct 03 03:08:35 AM UTC 24 |
| Peak memory | 3140604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879811048 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1879811048 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.588098035 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2519363398 ps |
| CPU time | 59.13 seconds |
| Started | Oct 03 02:10:31 AM UTC 24 |
| Finished | Oct 03 02:11:31 AM UTC 24 |
| Peak memory | 257000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588098035 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.588098035 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.213123776 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1370237560 ps |
| CPU time | 28.66 seconds |
| Started | Oct 03 02:10:36 AM UTC 24 |
| Finished | Oct 03 02:11:06 AM UTC 24 |
| Peak memory | 242528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213123776 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.213123776 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.4095350101 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 65674808754 ps |
| CPU time | 1404.22 seconds |
| Started | Oct 03 02:10:46 AM UTC 24 |
| Finished | Oct 03 02:34:28 AM UTC 24 |
| Peak memory | 1760228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095350101 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4095350101 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.1816246236 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 7312378987 ps |
| CPU time | 187.17 seconds |
| Started | Oct 03 02:10:47 AM UTC 24 |
| Finished | Oct 03 02:13:57 AM UTC 24 |
| Peak memory | 447460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816246236 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1816246236 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2187128356 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 88748937991 ps |
| CPU time | 3230.23 seconds |
| Started | Oct 03 02:11:01 AM UTC 24 |
| Finished | Oct 03 03:05:32 AM UTC 24 |
| Peak memory | 3066772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187128356 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2187128356 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.2474204965 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 22874036 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 03:35:42 AM UTC 24 |
| Finished | Oct 03 03:35:44 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474204965 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2474204965 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_app.2579357577 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3802719802 ps |
| CPU time | 116.68 seconds |
| Started | Oct 03 03:34:43 AM UTC 24 |
| Finished | Oct 03 03:36:42 AM UTC 24 |
| Peak memory | 300072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579357577 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2579357577 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.148647921 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 25678709510 ps |
| CPU time | 1465.99 seconds |
| Started | Oct 03 03:34:27 AM UTC 24 |
| Finished | Oct 03 03:59:12 AM UTC 24 |
| Peak memory | 271328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148647921 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.148647921 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.93937869 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 31304132649 ps |
| CPU time | 436.86 seconds |
| Started | Oct 03 03:35:00 AM UTC 24 |
| Finished | Oct 03 03:42:23 AM UTC 24 |
| Peak memory | 494628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93937869 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.93937869 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_error.2565451938 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2037265068 ps |
| CPU time | 59.64 seconds |
| Started | Oct 03 03:35:10 AM UTC 24 |
| Finished | Oct 03 03:36:11 AM UTC 24 |
| Peak memory | 277552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565451938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2565451938 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2042418127 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 15985617651 ps |
| CPU time | 31.02 seconds |
| Started | Oct 03 03:35:22 AM UTC 24 |
| Finished | Oct 03 03:35:55 AM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042418127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2042418127 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.2821397733 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 209814996 ps |
| CPU time | 4.04 seconds |
| Started | Oct 03 03:35:31 AM UTC 24 |
| Finished | Oct 03 03:35:36 AM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821397733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2821397733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.2022302391 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 7931776333 ps |
| CPU time | 282.05 seconds |
| Started | Oct 03 03:34:03 AM UTC 24 |
| Finished | Oct 03 03:38:50 AM UTC 24 |
| Peak memory | 351204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022302391 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.2022302391 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.3033153636 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 5037524405 ps |
| CPU time | 434.34 seconds |
| Started | Oct 03 03:34:17 AM UTC 24 |
| Finished | Oct 03 03:41:38 AM UTC 24 |
| Peak memory | 365600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033153636 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3033153636 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.213568448 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3077469807 ps |
| CPU time | 44.84 seconds |
| Started | Oct 03 03:33:55 AM UTC 24 |
| Finished | Oct 03 03:34:41 AM UTC 24 |
| Peak memory | 236588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213568448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.213568448 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.2585297780 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 65641645488 ps |
| CPU time | 849.32 seconds |
| Started | Oct 03 03:35:37 AM UTC 24 |
| Finished | Oct 03 03:49:57 AM UTC 24 |
| Peak memory | 361856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585297780 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2585297780 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.325892386 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 40333094 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 03:37:30 AM UTC 24 |
| Finished | Oct 03 03:37:32 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325892386 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.325892386 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_app.3267586340 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 29813254457 ps |
| CPU time | 285.57 seconds |
| Started | Oct 03 03:36:43 AM UTC 24 |
| Finished | Oct 03 03:41:33 AM UTC 24 |
| Peak memory | 412696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267586340 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3267586340 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.547739196 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 82079860081 ps |
| CPU time | 1535.1 seconds |
| Started | Oct 03 03:36:13 AM UTC 24 |
| Finished | Oct 03 04:02:07 AM UTC 24 |
| Peak memory | 273376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547739196 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.547739196 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.3409091369 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 33530605354 ps |
| CPU time | 226.59 seconds |
| Started | Oct 03 03:36:44 AM UTC 24 |
| Finished | Oct 03 03:40:35 AM UTC 24 |
| Peak memory | 377940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409091369 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3409091369 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_error.2657107292 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 18776659907 ps |
| CPU time | 702.79 seconds |
| Started | Oct 03 03:37:09 AM UTC 24 |
| Finished | Oct 03 03:49:02 AM UTC 24 |
| Peak memory | 582748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657107292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2657107292 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.3506436307 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2764884165 ps |
| CPU time | 9.52 seconds |
| Started | Oct 03 03:37:17 AM UTC 24 |
| Finished | Oct 03 03:37:27 AM UTC 24 |
| Peak memory | 230648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506436307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3506436307 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.1197443827 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 50515093 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 03:37:25 AM UTC 24 |
| Finished | Oct 03 03:37:29 AM UTC 24 |
| Peak memory | 234872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197443827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1197443827 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.445342859 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 47538639535 ps |
| CPU time | 2180.56 seconds |
| Started | Oct 03 03:35:45 AM UTC 24 |
| Finished | Oct 03 04:12:31 AM UTC 24 |
| Peak memory | 2341860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445342859 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.445342859 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.4036276770 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 9238754839 ps |
| CPU time | 517.67 seconds |
| Started | Oct 03 03:35:55 AM UTC 24 |
| Finished | Oct 03 03:44:40 AM UTC 24 |
| Peak memory | 357456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036276770 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.4036276770 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.2147782439 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1676951236 ps |
| CPU time | 90.38 seconds |
| Started | Oct 03 03:35:43 AM UTC 24 |
| Finished | Oct 03 03:37:15 AM UTC 24 |
| Peak memory | 236460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147782439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2147782439 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.2787651943 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 122289328529 ps |
| CPU time | 2500.02 seconds |
| Started | Oct 03 03:37:28 AM UTC 24 |
| Finished | Oct 03 04:19:39 AM UTC 24 |
| Peak memory | 1312128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787651943 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2787651943 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.1303681237 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 43170482 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 03:39:09 AM UTC 24 |
| Finished | Oct 03 03:39:11 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303681237 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1303681237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_app.353061274 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3647061610 ps |
| CPU time | 50.16 seconds |
| Started | Oct 03 03:38:25 AM UTC 24 |
| Finished | Oct 03 03:39:17 AM UTC 24 |
| Peak memory | 267552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353061274 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.353061274 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.3152188431 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 13018053957 ps |
| CPU time | 516.88 seconds |
| Started | Oct 03 03:38:10 AM UTC 24 |
| Finished | Oct 03 03:46:54 AM UTC 24 |
| Peak memory | 255068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152188431 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3152188431 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1785854212 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 14287015571 ps |
| CPU time | 135.69 seconds |
| Started | Oct 03 03:38:38 AM UTC 24 |
| Finished | Oct 03 03:40:56 AM UTC 24 |
| Peak memory | 275500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785854212 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1785854212 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_error.132652754 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 15584630440 ps |
| CPU time | 198.42 seconds |
| Started | Oct 03 03:38:43 AM UTC 24 |
| Finished | Oct 03 03:42:04 AM UTC 24 |
| Peak memory | 371948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132652754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.132652754 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.3864793385 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1144920382 ps |
| CPU time | 16.35 seconds |
| Started | Oct 03 03:38:51 AM UTC 24 |
| Finished | Oct 03 03:39:08 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864793385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3864793385 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.2584550904 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 102649193 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 03:39:02 AM UTC 24 |
| Finished | Oct 03 03:39:05 AM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584550904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2584550904 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1829191884 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 177493066191 ps |
| CPU time | 3344.28 seconds |
| Started | Oct 03 03:37:33 AM UTC 24 |
| Finished | Oct 03 04:33:58 AM UTC 24 |
| Peak memory | 3329056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829191884 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1829191884 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.135833931 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 14815151941 ps |
| CPU time | 88.95 seconds |
| Started | Oct 03 03:37:41 AM UTC 24 |
| Finished | Oct 03 03:39:12 AM UTC 24 |
| Peak memory | 277452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135833931 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.135833931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.29647569 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1160617797 ps |
| CPU time | 51.67 seconds |
| Started | Oct 03 03:37:31 AM UTC 24 |
| Finished | Oct 03 03:38:25 AM UTC 24 |
| Peak memory | 236584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29647569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.29647569 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.2107235395 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 11358709649 ps |
| CPU time | 120.39 seconds |
| Started | Oct 03 03:39:06 AM UTC 24 |
| Finished | Oct 03 03:41:09 AM UTC 24 |
| Peak memory | 286120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107235395 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2107235395 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.1908721459 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 28339519 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 03:41:22 AM UTC 24 |
| Finished | Oct 03 03:41:24 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908721459 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1908721459 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_app.2753077854 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1339481203 ps |
| CPU time | 57.25 seconds |
| Started | Oct 03 03:40:22 AM UTC 24 |
| Finished | Oct 03 03:41:21 AM UTC 24 |
| Peak memory | 263240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753077854 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2753077854 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.1261338697 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 169417709544 ps |
| CPU time | 1540.63 seconds |
| Started | Oct 03 03:40:08 AM UTC 24 |
| Finished | Oct 03 04:06:09 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261338697 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1261338697 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.3683259408 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 9566320441 ps |
| CPU time | 81.52 seconds |
| Started | Oct 03 03:40:36 AM UTC 24 |
| Finished | Oct 03 03:41:59 AM UTC 24 |
| Peak memory | 257064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683259408 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3683259408 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_error.1006583815 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 16190380245 ps |
| CPU time | 497.63 seconds |
| Started | Oct 03 03:40:57 AM UTC 24 |
| Finished | Oct 03 03:49:21 AM UTC 24 |
| Peak memory | 549916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006583815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1006583815 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.1911568658 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 4587813368 ps |
| CPU time | 5.85 seconds |
| Started | Oct 03 03:41:10 AM UTC 24 |
| Finished | Oct 03 03:41:17 AM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911568658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1911568658 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.3342597599 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 84604478 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 03:41:18 AM UTC 24 |
| Finished | Oct 03 03:41:21 AM UTC 24 |
| Peak memory | 232016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342597599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3342597599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.839501076 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 7825818804 ps |
| CPU time | 894.41 seconds |
| Started | Oct 03 03:39:13 AM UTC 24 |
| Finished | Oct 03 03:54:18 AM UTC 24 |
| Peak memory | 670800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839501076 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.839501076 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.2181898258 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 5899760739 ps |
| CPU time | 120.84 seconds |
| Started | Oct 03 03:39:18 AM UTC 24 |
| Finished | Oct 03 03:41:21 AM UTC 24 |
| Peak memory | 304156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181898258 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2181898258 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.4274207935 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 4384145073 ps |
| CPU time | 66.23 seconds |
| Started | Oct 03 03:39:13 AM UTC 24 |
| Finished | Oct 03 03:40:21 AM UTC 24 |
| Peak memory | 236824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274207935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.4274207935 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.336593423 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 33619382815 ps |
| CPU time | 1001.66 seconds |
| Started | Oct 03 03:41:22 AM UTC 24 |
| Finished | Oct 03 03:58:17 AM UTC 24 |
| Peak memory | 658856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336593423 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.336593423 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.399238642 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 26349826 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 03:42:25 AM UTC 24 |
| Finished | Oct 03 03:42:27 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399238642 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.399238642 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_app.4156619987 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 19041757523 ps |
| CPU time | 252.9 seconds |
| Started | Oct 03 03:41:39 AM UTC 24 |
| Finished | Oct 03 03:45:56 AM UTC 24 |
| Peak memory | 324584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156619987 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.4156619987 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.235386958 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 13010901295 ps |
| CPU time | 264.96 seconds |
| Started | Oct 03 03:41:35 AM UTC 24 |
| Finished | Oct 03 03:46:04 AM UTC 24 |
| Peak memory | 240608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235386958 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.235386958 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.1776267887 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 11998257725 ps |
| CPU time | 180.56 seconds |
| Started | Oct 03 03:41:57 AM UTC 24 |
| Finished | Oct 03 03:45:00 AM UTC 24 |
| Peak memory | 298012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776267887 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1776267887 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_error.3236973656 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 160054328400 ps |
| CPU time | 304.15 seconds |
| Started | Oct 03 03:42:00 AM UTC 24 |
| Finished | Oct 03 03:47:09 AM UTC 24 |
| Peak memory | 478252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236973656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3236973656 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.3934111288 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 14964560108 ps |
| CPU time | 23.83 seconds |
| Started | Oct 03 03:42:05 AM UTC 24 |
| Finished | Oct 03 03:42:30 AM UTC 24 |
| Peak memory | 228412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934111288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3934111288 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.3618599284 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 58009192 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 03:42:20 AM UTC 24 |
| Finished | Oct 03 03:42:24 AM UTC 24 |
| Peak memory | 234472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618599284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3618599284 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.984529152 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 27724060109 ps |
| CPU time | 3706.8 seconds |
| Started | Oct 03 03:41:25 AM UTC 24 |
| Finished | Oct 03 04:43:57 AM UTC 24 |
| Peak memory | 1815692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984529152 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.984529152 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.1509019326 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 32165537163 ps |
| CPU time | 230.95 seconds |
| Started | Oct 03 03:41:28 AM UTC 24 |
| Finished | Oct 03 03:45:23 AM UTC 24 |
| Peak memory | 414888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509019326 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.1509019326 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.2167023440 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 22731085889 ps |
| CPU time | 82.24 seconds |
| Started | Oct 03 03:41:22 AM UTC 24 |
| Finished | Oct 03 03:42:46 AM UTC 24 |
| Peak memory | 236592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167023440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2167023440 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.3566755496 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 323063170244 ps |
| CPU time | 2772.83 seconds |
| Started | Oct 03 03:42:24 AM UTC 24 |
| Finished | Oct 03 04:29:11 AM UTC 24 |
| Peak memory | 1738052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566755496 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3566755496 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.4097527639 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 40798828 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 03:45:43 AM UTC 24 |
| Finished | Oct 03 03:45:45 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097527639 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.4097527639 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_app.3990061153 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2682397127 ps |
| CPU time | 61.76 seconds |
| Started | Oct 03 03:44:00 AM UTC 24 |
| Finished | Oct 03 03:45:03 AM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990061153 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3990061153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.2682973704 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 6475334274 ps |
| CPU time | 383.36 seconds |
| Started | Oct 03 03:43:17 AM UTC 24 |
| Finished | Oct 03 03:49:46 AM UTC 24 |
| Peak memory | 240620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682973704 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2682973704 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.3218701245 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 27322205814 ps |
| CPU time | 217.23 seconds |
| Started | Oct 03 03:44:42 AM UTC 24 |
| Finished | Oct 03 03:48:22 AM UTC 24 |
| Peak memory | 369900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218701245 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3218701245 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_error.2281872235 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 45759057430 ps |
| CPU time | 471 seconds |
| Started | Oct 03 03:45:02 AM UTC 24 |
| Finished | Oct 03 03:53:00 AM UTC 24 |
| Peak memory | 498724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281872235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2281872235 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.3462921243 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1144354613 ps |
| CPU time | 7.15 seconds |
| Started | Oct 03 03:45:04 AM UTC 24 |
| Finished | Oct 03 03:45:12 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462921243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3462921243 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.522831007 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2992791785 ps |
| CPU time | 27.36 seconds |
| Started | Oct 03 03:45:13 AM UTC 24 |
| Finished | Oct 03 03:45:42 AM UTC 24 |
| Peak memory | 263416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522831007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.522831007 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.2247222003 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 16206560327 ps |
| CPU time | 410.41 seconds |
| Started | Oct 03 03:42:31 AM UTC 24 |
| Finished | Oct 03 03:49:28 AM UTC 24 |
| Peak memory | 480292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247222003 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.2247222003 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.2295899834 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 758074981 ps |
| CPU time | 27.32 seconds |
| Started | Oct 03 03:42:48 AM UTC 24 |
| Finished | Oct 03 03:43:16 AM UTC 24 |
| Peak memory | 244648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295899834 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2295899834 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.1554019337 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2368755296 ps |
| CPU time | 88.1 seconds |
| Started | Oct 03 03:42:28 AM UTC 24 |
| Finished | Oct 03 03:43:58 AM UTC 24 |
| Peak memory | 236820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554019337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1554019337 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.462317458 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 78971038047 ps |
| CPU time | 2530.86 seconds |
| Started | Oct 03 03:45:23 AM UTC 24 |
| Finished | Oct 03 04:28:07 AM UTC 24 |
| Peak memory | 1330468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462317458 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.462317458 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.1720042263 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 25745423 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 03:48:23 AM UTC 24 |
| Finished | Oct 03 03:48:25 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720042263 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1720042263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_app.1300168708 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 9010466607 ps |
| CPU time | 279.73 seconds |
| Started | Oct 03 03:46:55 AM UTC 24 |
| Finished | Oct 03 03:51:39 AM UTC 24 |
| Peak memory | 404568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300168708 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1300168708 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.4268096426 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4692324081 ps |
| CPU time | 282.63 seconds |
| Started | Oct 03 03:46:46 AM UTC 24 |
| Finished | Oct 03 03:51:33 AM UTC 24 |
| Peak memory | 240664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268096426 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.4268096426 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.756716683 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 46925578814 ps |
| CPU time | 322.28 seconds |
| Started | Oct 03 03:46:56 AM UTC 24 |
| Finished | Oct 03 03:52:23 AM UTC 24 |
| Peak memory | 472140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756716683 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.756716683 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_error.2430406144 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 35325374512 ps |
| CPU time | 438.57 seconds |
| Started | Oct 03 03:46:58 AM UTC 24 |
| Finished | Oct 03 03:54:23 AM UTC 24 |
| Peak memory | 474288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430406144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.2430406144 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.1071632141 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 464423254 ps |
| CPU time | 4.49 seconds |
| Started | Oct 03 03:47:09 AM UTC 24 |
| Finished | Oct 03 03:47:15 AM UTC 24 |
| Peak memory | 228384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071632141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1071632141 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.3250411617 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3836669286 ps |
| CPU time | 33.47 seconds |
| Started | Oct 03 03:47:16 AM UTC 24 |
| Finished | Oct 03 03:47:51 AM UTC 24 |
| Peak memory | 253036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250411617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3250411617 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2079091392 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 16092382097 ps |
| CPU time | 1833.79 seconds |
| Started | Oct 03 03:45:57 AM UTC 24 |
| Finished | Oct 03 04:16:55 AM UTC 24 |
| Peak memory | 1129504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079091392 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2079091392 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.3714278515 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 55740569838 ps |
| CPU time | 457.49 seconds |
| Started | Oct 03 03:46:04 AM UTC 24 |
| Finished | Oct 03 03:53:48 AM UTC 24 |
| Peak memory | 531432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714278515 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3714278515 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.900808303 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1038796956 ps |
| CPU time | 57.01 seconds |
| Started | Oct 03 03:45:46 AM UTC 24 |
| Finished | Oct 03 03:46:45 AM UTC 24 |
| Peak memory | 232720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900808303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.900808303 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.2879184808 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 285229508774 ps |
| CPU time | 2670.13 seconds |
| Started | Oct 03 03:47:52 AM UTC 24 |
| Finished | Oct 03 04:32:55 AM UTC 24 |
| Peak memory | 2282880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879184808 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2879184808 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.2015426041 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 28957291 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 03:51:15 AM UTC 24 |
| Finished | Oct 03 03:51:17 AM UTC 24 |
| Peak memory | 226648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015426041 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2015426041 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_app.3594025343 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3980897487 ps |
| CPU time | 179.28 seconds |
| Started | Oct 03 03:49:48 AM UTC 24 |
| Finished | Oct 03 03:52:50 AM UTC 24 |
| Peak memory | 277480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594025343 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3594025343 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.2036947054 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 28854107532 ps |
| CPU time | 671.87 seconds |
| Started | Oct 03 03:49:29 AM UTC 24 |
| Finished | Oct 03 04:00:50 AM UTC 24 |
| Peak memory | 246828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036947054 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2036947054 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1094670641 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4843334123 ps |
| CPU time | 197.43 seconds |
| Started | Oct 03 03:49:58 AM UTC 24 |
| Finished | Oct 03 03:53:19 AM UTC 24 |
| Peak memory | 302220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094670641 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1094670641 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_error.2570417098 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 18685186158 ps |
| CPU time | 736.3 seconds |
| Started | Oct 03 03:50:12 AM UTC 24 |
| Finished | Oct 03 04:02:38 AM UTC 24 |
| Peak memory | 619608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570417098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2570417098 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.1648222365 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1485751177 ps |
| CPU time | 19.18 seconds |
| Started | Oct 03 03:50:42 AM UTC 24 |
| Finished | Oct 03 03:51:03 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648222365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1648222365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.2596323384 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 101018166 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 03:51:04 AM UTC 24 |
| Finished | Oct 03 03:51:06 AM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596323384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2596323384 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.4248538227 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 81879197422 ps |
| CPU time | 529.02 seconds |
| Started | Oct 03 03:49:03 AM UTC 24 |
| Finished | Oct 03 03:57:59 AM UTC 24 |
| Peak memory | 685288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248538227 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.4248538227 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.4209115627 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5379097783 ps |
| CPU time | 455.12 seconds |
| Started | Oct 03 03:49:22 AM UTC 24 |
| Finished | Oct 03 03:57:04 AM UTC 24 |
| Peak memory | 375844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209115627 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.4209115627 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.4103875038 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 10101262820 ps |
| CPU time | 101.82 seconds |
| Started | Oct 03 03:48:27 AM UTC 24 |
| Finished | Oct 03 03:50:11 AM UTC 24 |
| Peak memory | 236696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103875038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.4103875038 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.2628301190 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 54032807284 ps |
| CPU time | 1133.71 seconds |
| Started | Oct 03 03:51:08 AM UTC 24 |
| Finished | Oct 03 04:10:17 AM UTC 24 |
| Peak memory | 486456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628301190 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2628301190 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.3717248599 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 19823099 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 03:53:09 AM UTC 24 |
| Finished | Oct 03 03:53:11 AM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717248599 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3717248599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_app.1621062898 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3085886607 ps |
| CPU time | 86.13 seconds |
| Started | Oct 03 03:52:19 AM UTC 24 |
| Finished | Oct 03 03:53:47 AM UTC 24 |
| Peak memory | 308248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621062898 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1621062898 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.154556216 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 149774800546 ps |
| CPU time | 1417.92 seconds |
| Started | Oct 03 03:51:43 AM UTC 24 |
| Finished | Oct 03 04:15:39 AM UTC 24 |
| Peak memory | 267216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154556216 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.154556216 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3308211236 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4036784319 ps |
| CPU time | 136.67 seconds |
| Started | Oct 03 03:52:24 AM UTC 24 |
| Finished | Oct 03 03:54:43 AM UTC 24 |
| Peak memory | 271380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308211236 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3308211236 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_error.2755872950 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 18689768586 ps |
| CPU time | 449.87 seconds |
| Started | Oct 03 03:52:51 AM UTC 24 |
| Finished | Oct 03 04:00:27 AM UTC 24 |
| Peak memory | 365792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755872950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2755872950 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.598139127 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1137614675 ps |
| CPU time | 13.98 seconds |
| Started | Oct 03 03:52:52 AM UTC 24 |
| Finished | Oct 03 03:53:07 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598139127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.598139127 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.3458191734 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 814061417 ps |
| CPU time | 18.79 seconds |
| Started | Oct 03 03:53:01 AM UTC 24 |
| Finished | Oct 03 03:53:21 AM UTC 24 |
| Peak memory | 246760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458191734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3458191734 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3106791736 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 10611643856 ps |
| CPU time | 1260.45 seconds |
| Started | Oct 03 03:51:34 AM UTC 24 |
| Finished | Oct 03 04:12:51 AM UTC 24 |
| Peak memory | 775136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106791736 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3106791736 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.2114223471 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 8331642602 ps |
| CPU time | 36.74 seconds |
| Started | Oct 03 03:51:40 AM UTC 24 |
| Finished | Oct 03 03:52:18 AM UTC 24 |
| Peak memory | 263144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114223471 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2114223471 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.631273240 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 464012150 ps |
| CPU time | 22.39 seconds |
| Started | Oct 03 03:51:18 AM UTC 24 |
| Finished | Oct 03 03:51:42 AM UTC 24 |
| Peak memory | 236448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631273240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.631273240 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.1772419592 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 10054337757 ps |
| CPU time | 716.55 seconds |
| Started | Oct 03 03:53:04 AM UTC 24 |
| Finished | Oct 03 04:05:10 AM UTC 24 |
| Peak memory | 380252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772419592 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1772419592 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.323689408 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 63056822 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 03:54:24 AM UTC 24 |
| Finished | Oct 03 03:54:26 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323689408 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.323689408 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_app.4181146531 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 16368274930 ps |
| CPU time | 216.4 seconds |
| Started | Oct 03 03:53:48 AM UTC 24 |
| Finished | Oct 03 03:57:28 AM UTC 24 |
| Peak memory | 392228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181146531 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.4181146531 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.1688546148 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 113471155848 ps |
| CPU time | 678.48 seconds |
| Started | Oct 03 03:53:34 AM UTC 24 |
| Finished | Oct 03 04:05:02 AM UTC 24 |
| Peak memory | 253020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688546148 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1688546148 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.4071229006 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4374018158 ps |
| CPU time | 163.74 seconds |
| Started | Oct 03 03:53:49 AM UTC 24 |
| Finished | Oct 03 03:56:36 AM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071229006 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.4071229006 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_error.2575443103 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4689823223 ps |
| CPU time | 41.75 seconds |
| Started | Oct 03 03:53:49 AM UTC 24 |
| Finished | Oct 03 03:54:32 AM UTC 24 |
| Peak memory | 263212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575443103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2575443103 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.3200136067 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 70692767 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 03:54:19 AM UTC 24 |
| Finished | Oct 03 03:54:23 AM UTC 24 |
| Peak memory | 228092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200136067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3200136067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.1578244284 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 66365895 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 03:54:22 AM UTC 24 |
| Finished | Oct 03 03:54:25 AM UTC 24 |
| Peak memory | 232452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578244284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1578244284 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.2807641335 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 16803466402 ps |
| CPU time | 743.48 seconds |
| Started | Oct 03 03:53:19 AM UTC 24 |
| Finished | Oct 03 04:05:52 AM UTC 24 |
| Peak memory | 990188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807641335 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.2807641335 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.1592153465 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 728405891 ps |
| CPU time | 22.96 seconds |
| Started | Oct 03 03:53:22 AM UTC 24 |
| Finished | Oct 03 03:53:47 AM UTC 24 |
| Peak memory | 253092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592153465 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1592153465 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.823939128 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5821553566 ps |
| CPU time | 66.89 seconds |
| Started | Oct 03 03:53:12 AM UTC 24 |
| Finished | Oct 03 03:54:21 AM UTC 24 |
| Peak memory | 236584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823939128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.823939128 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.2054082577 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 36585109385 ps |
| CPU time | 390.13 seconds |
| Started | Oct 03 03:54:24 AM UTC 24 |
| Finished | Oct 03 04:01:00 AM UTC 24 |
| Peak memory | 378208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054082577 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2054082577 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.1586938864 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 29357557 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 02:16:55 AM UTC 24 |
| Finished | Oct 03 02:16:57 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586938864 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1586938864 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_app.1290600061 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1391791185 ps |
| CPU time | 15.05 seconds |
| Started | Oct 03 02:13:57 AM UTC 24 |
| Finished | Oct 03 02:14:13 AM UTC 24 |
| Peak memory | 232872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290600061 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1290600061 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.3931518754 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 26792131110 ps |
| CPU time | 418.8 seconds |
| Started | Oct 03 02:13:58 AM UTC 24 |
| Finished | Oct 03 02:21:03 AM UTC 24 |
| Peak memory | 480296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931518754 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3931518754 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.1181960554 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 23053024478 ps |
| CPU time | 1229.96 seconds |
| Started | Oct 03 02:13:44 AM UTC 24 |
| Finished | Oct 03 02:34:30 AM UTC 24 |
| Peak memory | 267296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181960554 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1181960554 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.3935592232 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1283474743 ps |
| CPU time | 35.53 seconds |
| Started | Oct 03 02:16:04 AM UTC 24 |
| Finished | Oct 03 02:16:41 AM UTC 24 |
| Peak memory | 245760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935592232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3935592232 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.2109310196 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 27982769 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 02:16:08 AM UTC 24 |
| Finished | Oct 03 02:16:11 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109310196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2109310196 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.1177303770 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 470076764 ps |
| CPU time | 7.14 seconds |
| Started | Oct 03 02:16:11 AM UTC 24 |
| Finished | Oct 03 02:16:19 AM UTC 24 |
| Peak memory | 230652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177303770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1177303770 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.949301438 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13556251475 ps |
| CPU time | 106.1 seconds |
| Started | Oct 03 02:13:58 AM UTC 24 |
| Finished | Oct 03 02:15:47 AM UTC 24 |
| Peak memory | 285708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949301438 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.949301438 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_error.4116572740 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5054484079 ps |
| CPU time | 238.96 seconds |
| Started | Oct 03 02:15:12 AM UTC 24 |
| Finished | Oct 03 02:19:15 AM UTC 24 |
| Peak memory | 316524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116572740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.4116572740 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.1714342679 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3047983907 ps |
| CPU time | 13.72 seconds |
| Started | Oct 03 02:15:48 AM UTC 24 |
| Finished | Oct 03 02:16:03 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714342679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1714342679 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.900662897 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 290868581574 ps |
| CPU time | 4470.21 seconds |
| Started | Oct 03 02:13:34 AM UTC 24 |
| Finished | Oct 03 03:28:55 AM UTC 24 |
| Peak memory | 3857540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900662897 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.900662897 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.2746348501 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 48654235615 ps |
| CPU time | 519.92 seconds |
| Started | Oct 03 02:14:14 AM UTC 24 |
| Finished | Oct 03 02:23:01 AM UTC 24 |
| Peak memory | 554324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746348501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2746348501 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.3086822161 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5414713889 ps |
| CPU time | 320.06 seconds |
| Started | Oct 03 02:13:34 AM UTC 24 |
| Finished | Oct 03 02:18:58 AM UTC 24 |
| Peak memory | 332832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086822161 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3086822161 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.3674979543 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2893537159 ps |
| CPU time | 64.24 seconds |
| Started | Oct 03 02:12:50 AM UTC 24 |
| Finished | Oct 03 02:13:56 AM UTC 24 |
| Peak memory | 236780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674979543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3674979543 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.2293817276 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 13049020080 ps |
| CPU time | 460.41 seconds |
| Started | Oct 03 02:16:24 AM UTC 24 |
| Finished | Oct 03 02:24:11 AM UTC 24 |
| Peak memory | 293968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293817276 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2293817276 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.3046382122 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 47755469 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 02:21:03 AM UTC 24 |
| Finished | Oct 03 02:21:06 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046382122 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3046382122 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_app.3832232139 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 25615083580 ps |
| CPU time | 436.12 seconds |
| Started | Oct 03 02:18:11 AM UTC 24 |
| Finished | Oct 03 02:25:34 AM UTC 24 |
| Peak memory | 373744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832232139 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3832232139 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1157271716 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 24483417866 ps |
| CPU time | 345.88 seconds |
| Started | Oct 03 02:18:27 AM UTC 24 |
| Finished | Oct 03 02:24:17 AM UTC 24 |
| Peak memory | 484584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157271716 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1157271716 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.526494113 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1513447212 ps |
| CPU time | 218.27 seconds |
| Started | Oct 03 02:17:47 AM UTC 24 |
| Finished | Oct 03 02:21:29 AM UTC 24 |
| Peak memory | 236444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526494113 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.526494113 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.4097236135 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 5605490966 ps |
| CPU time | 50.87 seconds |
| Started | Oct 03 02:20:37 AM UTC 24 |
| Finished | Oct 03 02:21:29 AM UTC 24 |
| Peak memory | 246556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097236135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.4097236135 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.77038403 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 73585955 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 02:20:42 AM UTC 24 |
| Finished | Oct 03 02:20:44 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77038403 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.77038403 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.4023254943 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 16521778073 ps |
| CPU time | 61.34 seconds |
| Started | Oct 03 02:20:45 AM UTC 24 |
| Finished | Oct 03 02:21:48 AM UTC 24 |
| Peak memory | 236564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023254943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.4023254943 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3900319023 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 162704588007 ps |
| CPU time | 395.75 seconds |
| Started | Oct 03 02:19:00 AM UTC 24 |
| Finished | Oct 03 02:25:41 AM UTC 24 |
| Peak memory | 441572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900319023 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3900319023 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_error.1670408898 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 67565145326 ps |
| CPU time | 466.32 seconds |
| Started | Oct 03 02:19:16 AM UTC 24 |
| Finished | Oct 03 02:27:09 AM UTC 24 |
| Peak memory | 576748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670408898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1670408898 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.1817848043 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 474673977 ps |
| CPU time | 6.77 seconds |
| Started | Oct 03 02:20:28 AM UTC 24 |
| Finished | Oct 03 02:20:36 AM UTC 24 |
| Peak memory | 230360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817848043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1817848043 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.3840333782 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 131754300 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 02:20:49 AM UTC 24 |
| Finished | Oct 03 02:20:52 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840333782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3840333782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.2379613218 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 89586643168 ps |
| CPU time | 3539.81 seconds |
| Started | Oct 03 02:17:08 AM UTC 24 |
| Finished | Oct 03 03:16:49 AM UTC 24 |
| Peak memory | 3728424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379613218 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2379613218 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.99527737 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3328041515 ps |
| CPU time | 104.76 seconds |
| Started | Oct 03 02:19:01 AM UTC 24 |
| Finished | Oct 03 02:20:48 AM UTC 24 |
| Peak memory | 298348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99527737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.99527737 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.4215679583 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 19553431925 ps |
| CPU time | 166.52 seconds |
| Started | Oct 03 02:17:37 AM UTC 24 |
| Finished | Oct 03 02:20:27 AM UTC 24 |
| Peak memory | 341004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215679583 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.4215679583 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.4068201263 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1722523712 ps |
| CPU time | 70.77 seconds |
| Started | Oct 03 02:16:58 AM UTC 24 |
| Finished | Oct 03 02:18:10 AM UTC 24 |
| Peak memory | 236424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068201263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.4068201263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.3619647160 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 16154201037 ps |
| CPU time | 1037.68 seconds |
| Started | Oct 03 02:20:53 AM UTC 24 |
| Finished | Oct 03 02:38:23 AM UTC 24 |
| Peak memory | 542284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619647160 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3619647160 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.3472090657 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 13188608 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 02:25:11 AM UTC 24 |
| Finished | Oct 03 02:25:13 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472090657 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3472090657 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_app.740356861 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5767845883 ps |
| CPU time | 324.24 seconds |
| Started | Oct 03 02:21:49 AM UTC 24 |
| Finished | Oct 03 02:27:18 AM UTC 24 |
| Peak memory | 326696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740356861 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.740356861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.3880022703 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 36714474748 ps |
| CPU time | 407 seconds |
| Started | Oct 03 02:23:02 AM UTC 24 |
| Finished | Oct 03 02:29:55 AM UTC 24 |
| Peak memory | 336872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880022703 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.3880022703 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.1067106841 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 29805427408 ps |
| CPU time | 1374.84 seconds |
| Started | Oct 03 02:21:30 AM UTC 24 |
| Finished | Oct 03 02:44:41 AM UTC 24 |
| Peak memory | 265484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067106841 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1067106841 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2308530666 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 48002365 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 02:24:40 AM UTC 24 |
| Finished | Oct 03 02:24:43 AM UTC 24 |
| Peak memory | 228284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308530666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2308530666 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.610868467 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 69897452 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 02:24:44 AM UTC 24 |
| Finished | Oct 03 02:24:47 AM UTC 24 |
| Peak memory | 228284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610868467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.610868467 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.3453441673 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 78957349 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 02:24:46 AM UTC 24 |
| Finished | Oct 03 02:24:48 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453441673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3453441673 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.2474286101 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 14662912099 ps |
| CPU time | 97.81 seconds |
| Started | Oct 03 02:23:55 AM UTC 24 |
| Finished | Oct 03 02:25:35 AM UTC 24 |
| Peak memory | 298088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474286101 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2474286101 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_error.3061731733 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4387766082 ps |
| CPU time | 279.41 seconds |
| Started | Oct 03 02:24:18 AM UTC 24 |
| Finished | Oct 03 02:29:02 AM UTC 24 |
| Peak memory | 338984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061731733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3061731733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.604818610 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1383395757 ps |
| CPU time | 19.49 seconds |
| Started | Oct 03 02:24:19 AM UTC 24 |
| Finished | Oct 03 02:24:40 AM UTC 24 |
| Peak memory | 230360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604818610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.604818610 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.4118672075 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 414686987711 ps |
| CPU time | 4394.48 seconds |
| Started | Oct 03 02:21:16 AM UTC 24 |
| Finished | Oct 03 03:35:21 AM UTC 24 |
| Peak memory | 4254900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118672075 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.4118672075 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.625054058 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 48123155561 ps |
| CPU time | 475.42 seconds |
| Started | Oct 03 02:24:12 AM UTC 24 |
| Finished | Oct 03 02:32:14 AM UTC 24 |
| Peak memory | 355836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625054058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.625054058 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.258633336 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 4712012281 ps |
| CPU time | 165.53 seconds |
| Started | Oct 03 02:21:30 AM UTC 24 |
| Finished | Oct 03 02:24:18 AM UTC 24 |
| Peak memory | 349460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258633336 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.258633336 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.3328590228 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 156126650 ps |
| CPU time | 6.81 seconds |
| Started | Oct 03 02:21:07 AM UTC 24 |
| Finished | Oct 03 02:21:15 AM UTC 24 |
| Peak memory | 236652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328590228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3328590228 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.184005272 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 84981785454 ps |
| CPU time | 915.92 seconds |
| Started | Oct 03 02:24:49 AM UTC 24 |
| Finished | Oct 03 02:40:17 AM UTC 24 |
| Peak memory | 1181248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184005272 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.184005272 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.3012069892 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 23551841209 ps |
| CPU time | 243.63 seconds |
| Started | Oct 03 02:24:53 AM UTC 24 |
| Finished | Oct 03 02:29:00 AM UTC 24 |
| Peak memory | 302784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_02 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3012069892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_r and_reset.3012069892 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.483536823 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 26114739 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 02:29:44 AM UTC 24 |
| Finished | Oct 03 02:29:46 AM UTC 24 |
| Peak memory | 226656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483536823 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.483536823 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_app.2346493119 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 17862720394 ps |
| CPU time | 338.96 seconds |
| Started | Oct 03 02:25:45 AM UTC 24 |
| Finished | Oct 03 02:31:29 AM UTC 24 |
| Peak memory | 412696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346493119 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2346493119 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2909847874 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 85604237459 ps |
| CPU time | 342.56 seconds |
| Started | Oct 03 02:27:10 AM UTC 24 |
| Finished | Oct 03 02:32:58 AM UTC 24 |
| Peak memory | 418848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909847874 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2909847874 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.2850610276 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 53845131460 ps |
| CPU time | 1500.6 seconds |
| Started | Oct 03 02:25:42 AM UTC 24 |
| Finished | Oct 03 02:51:03 AM UTC 24 |
| Peak memory | 256996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850610276 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2850610276 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.359577425 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1229521624 ps |
| CPU time | 39.54 seconds |
| Started | Oct 03 02:29:02 AM UTC 24 |
| Finished | Oct 03 02:29:43 AM UTC 24 |
| Peak memory | 246440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359577425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.359577425 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.3255918201 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 16019422 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 02:29:08 AM UTC 24 |
| Finished | Oct 03 02:29:11 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255918201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3255918201 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.1041770140 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2292874113 ps |
| CPU time | 22.93 seconds |
| Started | Oct 03 02:29:12 AM UTC 24 |
| Finished | Oct 03 02:29:37 AM UTC 24 |
| Peak memory | 236588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041770140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1041770140 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.235452568 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 15747124201 ps |
| CPU time | 193.43 seconds |
| Started | Oct 03 02:27:19 AM UTC 24 |
| Finished | Oct 03 02:30:36 AM UTC 24 |
| Peak memory | 283932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235452568 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.235452568 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_error.303061281 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 89341441171 ps |
| CPU time | 417.95 seconds |
| Started | Oct 03 02:28:47 AM UTC 24 |
| Finished | Oct 03 02:35:51 AM UTC 24 |
| Peak memory | 418844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303061281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.303061281 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.3241982469 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 302964795 ps |
| CPU time | 4.21 seconds |
| Started | Oct 03 02:29:01 AM UTC 24 |
| Finished | Oct 03 02:29:07 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241982469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3241982469 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.79042933 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 78791040 ps |
| CPU time | 2.89 seconds |
| Started | Oct 03 02:29:38 AM UTC 24 |
| Finished | Oct 03 02:29:41 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79042933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.79042933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2040060733 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 14829118267 ps |
| CPU time | 1859.74 seconds |
| Started | Oct 03 02:25:34 AM UTC 24 |
| Finished | Oct 03 02:56:56 AM UTC 24 |
| Peak memory | 1068008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040060733 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2040060733 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.3581448596 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 26710934385 ps |
| CPU time | 216.62 seconds |
| Started | Oct 03 02:28:36 AM UTC 24 |
| Finished | Oct 03 02:32:16 AM UTC 24 |
| Peak memory | 392736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581448596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3581448596 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2756745418 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 40294268504 ps |
| CPU time | 362.46 seconds |
| Started | Oct 03 02:25:36 AM UTC 24 |
| Finished | Oct 03 02:31:44 AM UTC 24 |
| Peak memory | 478508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756745418 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2756745418 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.869149655 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1496427175 ps |
| CPU time | 28.87 seconds |
| Started | Oct 03 02:25:14 AM UTC 24 |
| Finished | Oct 03 02:25:44 AM UTC 24 |
| Peak memory | 236428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869149655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.869149655 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.24239027 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 31028538814 ps |
| CPU time | 2870.21 seconds |
| Started | Oct 03 02:29:41 AM UTC 24 |
| Finished | Oct 03 03:18:04 AM UTC 24 |
| Peak memory | 836924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24239027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.24239027 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.2622034962 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 20572646 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 02:32:22 AM UTC 24 |
| Finished | Oct 03 02:32:24 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622034962 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2622034962 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_app.1727715738 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 16268525028 ps |
| CPU time | 179.58 seconds |
| Started | Oct 03 02:30:37 AM UTC 24 |
| Finished | Oct 03 02:33:40 AM UTC 24 |
| Peak memory | 326700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727715738 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1727715738 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.2956422686 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 9136734733 ps |
| CPU time | 282.72 seconds |
| Started | Oct 03 02:30:55 AM UTC 24 |
| Finished | Oct 03 02:35:42 AM UTC 24 |
| Peak memory | 318484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956422686 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2956422686 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.2000314371 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 109036544326 ps |
| CPU time | 1048.27 seconds |
| Started | Oct 03 02:30:36 AM UTC 24 |
| Finished | Oct 03 02:48:18 AM UTC 24 |
| Peak memory | 265228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000314371 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2000314371 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.411033922 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 17727589 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 02:31:58 AM UTC 24 |
| Finished | Oct 03 02:32:00 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411033922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.411033922 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3831356267 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 33719033 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 02:32:01 AM UTC 24 |
| Finished | Oct 03 02:32:04 AM UTC 24 |
| Peak memory | 228344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831356267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3831356267 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.1861303551 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1616108298 ps |
| CPU time | 5.54 seconds |
| Started | Oct 03 02:32:05 AM UTC 24 |
| Finished | Oct 03 02:32:12 AM UTC 24 |
| Peak memory | 230620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861303551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1861303551 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.2065362268 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6182651161 ps |
| CPU time | 100.36 seconds |
| Started | Oct 03 02:30:57 AM UTC 24 |
| Finished | Oct 03 02:32:39 AM UTC 24 |
| Peak memory | 255060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065362268 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2065362268 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_error.1369571457 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 64945944454 ps |
| CPU time | 418.91 seconds |
| Started | Oct 03 02:31:33 AM UTC 24 |
| Finished | Oct 03 02:38:37 AM UTC 24 |
| Peak memory | 371732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369571457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1369571457 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.3791796611 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1445959955 ps |
| CPU time | 10.84 seconds |
| Started | Oct 03 02:31:45 AM UTC 24 |
| Finished | Oct 03 02:31:57 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791796611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3791796611 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.2190884638 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 316311496 ps |
| CPU time | 6.54 seconds |
| Started | Oct 03 02:32:13 AM UTC 24 |
| Finished | Oct 03 02:32:21 AM UTC 24 |
| Peak memory | 236392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190884638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2190884638 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.450926639 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1359684654 ps |
| CPU time | 61.55 seconds |
| Started | Oct 03 02:29:53 AM UTC 24 |
| Finished | Oct 03 02:30:56 AM UTC 24 |
| Peak memory | 263020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450926639 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.450926639 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.44565987 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6927433166 ps |
| CPU time | 368.33 seconds |
| Started | Oct 03 02:31:30 AM UTC 24 |
| Finished | Oct 03 02:37:43 AM UTC 24 |
| Peak memory | 355872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44565987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.44565987 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.2670831441 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 36320656449 ps |
| CPU time | 219.16 seconds |
| Started | Oct 03 02:29:56 AM UTC 24 |
| Finished | Oct 03 02:33:39 AM UTC 24 |
| Peak memory | 361708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670831441 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2670831441 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.689651942 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 221764089 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 02:29:47 AM UTC 24 |
| Finished | Oct 03 02:29:52 AM UTC 24 |
| Peak memory | 236428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689651942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.689651942 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.3569472808 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 17218241960 ps |
| CPU time | 261.32 seconds |
| Started | Oct 03 02:32:15 AM UTC 24 |
| Finished | Oct 03 02:36:41 AM UTC 24 |
| Peak memory | 288116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569472808 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3569472808 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/9.kmac_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |