Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175251 |
1 |
|
|
T8 |
284 |
|
T4 |
1611 |
|
T12 |
121 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92275 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60951 |
1 |
|
|
T8 |
5 |
|
T4 |
1585 |
|
T12 |
7 |
seven_bytes |
3188 |
1 |
|
|
T8 |
4 |
|
T12 |
3 |
|
T13 |
65 |
six_bytes |
3115 |
1 |
|
|
T8 |
5 |
|
T12 |
3 |
|
T13 |
48 |
five_bytes |
3168 |
1 |
|
|
T8 |
7 |
|
T12 |
5 |
|
T13 |
56 |
four_bytes |
3231 |
1 |
|
|
T8 |
4 |
|
T12 |
1 |
|
T13 |
54 |
three_bytes |
3097 |
1 |
|
|
T8 |
7 |
|
T12 |
2 |
|
T13 |
51 |
two_bytes |
3158 |
1 |
|
|
T8 |
12 |
|
T12 |
9 |
|
T13 |
48 |
one_byte |
3068 |
1 |
|
|
T8 |
8 |
|
T12 |
1 |
|
T13 |
40 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171990 |
1 |
|
|
T8 |
282 |
|
T4 |
1559 |
|
T12 |
119 |
auto[1] |
3261 |
1 |
|
|
T8 |
2 |
|
T4 |
52 |
|
T12 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175251 |
1 |
|
|
T8 |
284 |
|
T4 |
1611 |
|
T12 |
121 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175238 |
1 |
|
|
T8 |
284 |
|
T4 |
1611 |
|
T12 |
121 |
auto[1] |
13 |
1 |
|
|
T25 |
1 |
|
T185 |
1 |
|
T60 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1121 |
1 |
|
|
T8 |
1 |
|
T4 |
26 |
|
T12 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3261 |
1 |
|
|
T8 |
2 |
|
T4 |
52 |
|
T12 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165680 |
1 |
|
|
T8 |
105 |
|
T4 |
1072 |
|
T11 |
223 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
82276 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
64078 |
1 |
|
|
T8 |
2 |
|
T4 |
1055 |
|
T11 |
220 |
seven_bytes |
2861 |
1 |
|
|
T12 |
8 |
|
T13 |
36 |
|
T42 |
15 |
six_bytes |
2709 |
1 |
|
|
T8 |
2 |
|
T12 |
5 |
|
T13 |
44 |
five_bytes |
2756 |
1 |
|
|
T8 |
2 |
|
T12 |
7 |
|
T13 |
31 |
four_bytes |
2785 |
1 |
|
|
T8 |
6 |
|
T12 |
12 |
|
T13 |
36 |
three_bytes |
2752 |
1 |
|
|
T8 |
4 |
|
T12 |
2 |
|
T13 |
41 |
two_bytes |
2734 |
1 |
|
|
T8 |
3 |
|
T12 |
5 |
|
T13 |
34 |
one_byte |
2729 |
1 |
|
|
T8 |
3 |
|
T12 |
6 |
|
T13 |
43 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162426 |
1 |
|
|
T8 |
103 |
|
T4 |
1038 |
|
T11 |
217 |
auto[1] |
3254 |
1 |
|
|
T8 |
2 |
|
T4 |
34 |
|
T11 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165680 |
1 |
|
|
T8 |
105 |
|
T4 |
1072 |
|
T11 |
223 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165670 |
1 |
|
|
T8 |
105 |
|
T4 |
1072 |
|
T11 |
223 |
auto[1] |
10 |
1 |
|
|
T5 |
1 |
|
T186 |
2 |
|
T187 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1148 |
1 |
|
|
T4 |
17 |
|
T11 |
3 |
|
T5 |
52 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3254 |
1 |
|
|
T8 |
2 |
|
T4 |
34 |
|
T11 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345271 |
1 |
|
|
T8 |
577 |
|
T4 |
3182 |
|
T11 |
112 |
auto[1] |
523 |
1 |
|
|
T4 |
56 |
|
T5 |
102 |
|
T6 |
7 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
180006 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
123213 |
1 |
|
|
T8 |
18 |
|
T4 |
3182 |
|
T11 |
110 |
seven_bytes |
6149 |
1 |
|
|
T8 |
18 |
|
T12 |
21 |
|
T13 |
58 |
six_bytes |
6177 |
1 |
|
|
T8 |
14 |
|
T12 |
21 |
|
T13 |
51 |
five_bytes |
6141 |
1 |
|
|
T8 |
13 |
|
T12 |
16 |
|
T13 |
75 |
four_bytes |
5999 |
1 |
|
|
T8 |
13 |
|
T12 |
22 |
|
T13 |
53 |
three_bytes |
6146 |
1 |
|
|
T8 |
15 |
|
T12 |
21 |
|
T13 |
42 |
two_bytes |
5885 |
1 |
|
|
T8 |
18 |
|
T12 |
22 |
|
T13 |
61 |
one_byte |
6078 |
1 |
|
|
T8 |
23 |
|
T12 |
22 |
|
T13 |
60 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339206 |
1 |
|
|
T8 |
573 |
|
T4 |
3126 |
|
T11 |
108 |
auto[1] |
6588 |
1 |
|
|
T8 |
4 |
|
T4 |
112 |
|
T11 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345794 |
1 |
|
|
T8 |
577 |
|
T4 |
3238 |
|
T11 |
112 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345772 |
1 |
|
|
T8 |
577 |
|
T4 |
3236 |
|
T11 |
112 |
auto[1] |
22 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T66 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2280 |
1 |
|
|
T4 |
56 |
|
T11 |
2 |
|
T12 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6588 |
1 |
|
|
T8 |
4 |
|
T4 |
112 |
|
T11 |
4 |