Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50879647	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

48657282

1

T1

316

T2

297

T3

151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55014243	1			T1	231		T2	213		T3	52
values[0x0]	21553696	1			T1	160		T2	145		T3	61
values[0x1]	22968990	1			T1	163		T2	174		T3	97

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39100460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60436469

1

T1

370

T2

346

T3

168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	543577	1			T8	2		T18	31		T38	31
valid_sources[0x01]	289859	1			T2	1		T8	2		T18	16
valid_sources[0x02]	288824	1			T2	1		T8	4		T18	20
valid_sources[0x03]	456487	1			T8	1		T18	19		T38	25
valid_sources[0x04]	290397	1			T2	4		T9	231		T18	24
valid_sources[0x05]	291439	1			T2	3		T8	4		T18	15
valid_sources[0x06]	315948	1			T8	1		T18	15		T38	24
valid_sources[0x07]	292332	1			T2	1		T8	4		T18	9
valid_sources[0x08]	293663	1			T3	3		T18	26		T38	27
valid_sources[0x09]	316463	1			T2	4		T3	17		T8	4
valid_sources[0x0a]	348347	1			T2	1		T8	1		T18	19
valid_sources[0x0b]	284389	1			T2	5		T18	19		T38	35
valid_sources[0x0c]	293234	1			T2	6		T8	4		T18	22
valid_sources[0x0d]	435275	1			T8	3		T18	14		T38	39
valid_sources[0x0e]	305438	1			T2	8		T3	4		T8	1
valid_sources[0x0f]	291077	1			T2	1		T8	1		T18	10
valid_sources[0x10]	288569	1			T18	25		T38	36		T4	17
valid_sources[0x11]	1164296	1			T2	2		T8	4		T18	9
valid_sources[0x12]	292323	1			T8	1		T18	20		T38	29
valid_sources[0x13]	490940	1			T8	1		T18	27		T38	25
valid_sources[0x14]	393845	1			T2	1		T18	22		T38	30
valid_sources[0x15]	814513	1			T2	4		T8	3		T18	15
valid_sources[0x16]	293004	1			T2	1		T8	3		T18	21
valid_sources[0x17]	289900	1			T2	2		T8	1		T18	24
valid_sources[0x18]	294496	1			T2	6		T8	2		T18	17
valid_sources[0x19]	291458	1			T2	3		T18	23		T38	31
valid_sources[0x1a]	286901	1			T2	6		T8	3		T18	25
valid_sources[0x1b]	289016	1			T2	2		T8	1		T18	28
valid_sources[0x1c]	286982	1			T8	2		T18	23		T40	2
valid_sources[0x1d]	288946	1			T2	4		T8	1		T18	17
valid_sources[0x1e]	290876	1			T8	3		T18	16		T38	23
valid_sources[0x1f]	290116	1			T2	1		T3	3		T8	2
valid_sources[0x20]	291369	1			T8	1		T18	17		T38	28
valid_sources[0x21]	292101	1			T2	5		T8	2		T18	35
valid_sources[0x22]	400618	1			T2	3		T8	1		T18	20
valid_sources[0x23]	295682	1			T8	4		T18	12		T38	33
valid_sources[0x24]	292409	1			T3	1		T8	2		T18	18
valid_sources[0x25]	282761	1			T2	1		T8	2		T18	29
valid_sources[0x26]	291573	1			T2	4		T8	3		T18	26
valid_sources[0x27]	411104	1			T2	1		T18	11		T38	29
valid_sources[0x28]	290122	1			T2	1		T8	2		T18	15
valid_sources[0x29]	284616	1			T2	2		T8	3		T18	10
valid_sources[0x2a]	515629	1			T8	3		T18	19		T38	26
valid_sources[0x2b]	292224	1			T2	8		T8	1		T18	27
valid_sources[0x2c]	661602	1			T2	2		T8	1		T18	14
valid_sources[0x2d]	289722	1			T18	19		T38	24		T4	50
valid_sources[0x2e]	284083	1			T2	5		T8	1		T18	18
valid_sources[0x2f]	288354	1			T2	5		T8	1		T18	18
valid_sources[0x30]	338123	1			T3	6		T39	156		T8	3
valid_sources[0x31]	1181061	1			T8	2		T18	15		T38	20
valid_sources[0x32]	1335346	1			T2	1		T8	4		T18	13
valid_sources[0x33]	287270	1			T3	1		T18	24		T38	25
valid_sources[0x34]	469548	1			T2	13		T8	5		T18	15
valid_sources[0x35]	289583	1			T2	2		T3	4		T8	4
valid_sources[0x36]	508179	1			T8	3		T18	14		T38	31
valid_sources[0x37]	290324	1			T8	3		T18	30		T38	27
valid_sources[0x38]	291042	1			T2	3		T8	1		T18	22
valid_sources[0x39]	285091	1			T3	2		T8	4		T18	16
valid_sources[0x3a]	470144	1			T8	4		T18	16		T38	27
valid_sources[0x3b]	591471	1			T2	11		T8	4		T18	16
valid_sources[0x3c]	494565	1			T2	2		T8	2		T18	15
valid_sources[0x3d]	287672	1			T2	3		T8	3		T18	9
valid_sources[0x3e]	1243294	1			T2	2		T8	2		T18	26
valid_sources[0x3f]	949138	1			T2	1		T8	2		T18	20
valid_sources[0x40]	292377	1			T2	4		T8	1		T18	22
valid_sources[0x41]	289504	1			T2	2		T8	1		T18	27
valid_sources[0x42]	289398	1			T2	1		T8	3		T18	17
valid_sources[0x43]	296021	1			T2	2		T18	15		T38	23
valid_sources[0x44]	316680	1			T2	7		T8	2		T18	14
valid_sources[0x45]	291932	1			T8	4		T18	18		T38	23
valid_sources[0x46]	336124	1			T2	1		T8	7		T18	21
valid_sources[0x47]	289697	1			T2	3		T8	1		T18	19
valid_sources[0x48]	291066	1			T8	1		T18	16		T38	27
valid_sources[0x49]	323654	1			T2	1		T18	20		T38	18
valid_sources[0x4a]	287675	1			T2	1		T8	2		T18	17
valid_sources[0x4b]	316834	1			T2	2		T8	5		T18	15
valid_sources[0x4c]	292724	1			T2	5		T8	2		T18	15
valid_sources[0x4d]	288143	1			T2	3		T8	3		T18	22
valid_sources[0x4e]	291181	1			T2	3		T8	2		T18	23
valid_sources[0x4f]	287377	1			T2	4		T8	5		T18	10
valid_sources[0x50]	460450	1			T3	2		T8	1		T18	29
valid_sources[0x51]	293889	1			T2	1		T8	2		T18	21
valid_sources[0x52]	289126	1			T2	1		T8	1		T18	19
valid_sources[0x53]	286094	1			T8	5		T18	28		T38	20
valid_sources[0x54]	305156	1			T3	15		T8	3		T18	20
valid_sources[0x55]	347441	1			T2	1		T18	12		T38	18
valid_sources[0x56]	291054	1			T2	3		T3	4		T8	3
valid_sources[0x57]	289190	1			T2	5		T8	6		T18	20
valid_sources[0x58]	288796	1			T2	3		T8	1		T18	11
valid_sources[0x59]	287961	1			T8	1		T18	17		T38	26
valid_sources[0x5a]	288531	1			T2	1		T8	1		T18	11
valid_sources[0x5b]	290285	1			T8	1		T18	18		T38	20
valid_sources[0x5c]	285075	1			T2	1		T8	3		T18	5
valid_sources[0x5d]	288476	1			T3	3		T18	21		T38	22
valid_sources[0x5e]	1360205	1			T2	1		T8	1		T18	14
valid_sources[0x5f]	474925	1			T2	2		T8	1		T18	26
valid_sources[0x60]	394591	1			T2	4		T8	2		T18	18
valid_sources[0x61]	285923	1			T2	2		T8	1		T18	24
valid_sources[0x62]	322441	1			T2	2		T8	3		T18	20
valid_sources[0x63]	322830	1			T2	2		T8	6		T18	15
valid_sources[0x64]	293615	1			T2	4		T3	3		T8	2
valid_sources[0x65]	475446	1			T8	1		T18	9		T38	38
valid_sources[0x66]	361243	1			T2	1		T8	3		T18	16
valid_sources[0x67]	292363	1			T2	2		T8	1		T18	13
valid_sources[0x68]	566496	1			T2	5		T18	27		T38	30
valid_sources[0x69]	291043	1			T8	2		T18	18		T38	20
valid_sources[0x6a]	1021882	1			T2	1		T8	2		T18	17
valid_sources[0x6b]	288879	1			T8	1		T18	14		T38	18
valid_sources[0x6c]	289690	1			T2	1		T3	10		T8	2
valid_sources[0x6d]	289373	1			T2	1		T3	2		T8	3
valid_sources[0x6e]	1319389	1			T2	1		T8	2		T18	19
valid_sources[0x6f]	294941	1			T8	2		T18	22		T38	23
valid_sources[0x70]	346123	1			T18	30		T38	33		T4	16
valid_sources[0x71]	284911	1			T2	2		T18	19		T38	20
valid_sources[0x72]	289700	1			T8	1		T18	18		T38	29
valid_sources[0x73]	290838	1			T2	2		T8	2		T18	13
valid_sources[0x74]	1410792	1			T2	2		T18	25		T38	31
valid_sources[0x75]	349464	1			T2	7		T18	18		T38	30
valid_sources[0x76]	359972	1			T2	2		T8	2		T18	16
valid_sources[0x77]	291056	1			T2	3		T8	2886		T18	21
valid_sources[0x78]	1003928	1			T2	4		T8	2		T18	24
valid_sources[0x79]	604552	1			T8	1		T18	24		T38	24
valid_sources[0x7a]	288127	1			T2	6		T18	15		T38	20
valid_sources[0x7b]	287690	1			T2	6		T8	3		T18	18
valid_sources[0x7c]	289561	1			T2	6		T8	4		T18	21
valid_sources[0x7d]	288637	1			T2	1		T8	1		T18	25
valid_sources[0x7e]	288824	1			T2	5		T8	4		T18	29
valid_sources[0x7f]	337916	1			T2	3		T18	15		T38	28
valid_sources[0x80]	290754	1			T8	1		T18	27		T38	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21175792

1

T1

110

T2

89

T3

4

values[0x0]

all_enables

biggest_size

14447183

1

T1

107

T2

104

T3

57

values[0x1]

all_enables

biggest_size

13034307

1

T1

99

T2

104

T3

90