Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50984059

1

T1

238

T2

235

T3

59

full_word

48663725

1

T1

316

T2

297

T3

151

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	99647464	1			T1	554		T2	532		T3	210
auto[TlIntgErrCmd]	102	1			T132	4		T133	3		T134	7
auto[TlIntgErrData]	111	1			T132	2		T133	5		T134	7
auto[TlIntgErrBoth]	107	1			T132	4		T133	2		T134	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55038239

1

T1

231

T2

213

T3

52

auto[1]

44609545

1

T1

323

T2

319

T3

158

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	33860450	1			T1	121		T2	124		T3	48
auto[TlIntgErrNone]	partial	auto[1]	17123319	1			T1	117		T2	111		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	21177653	1			T1	110		T2	89		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	27486042	1			T1	206		T2	208		T3	147
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T133	1		T134	2		T188	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T132	4		T133	2		T134	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T189	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T190	2		T191	1		T192	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T132	2		T133	3		T134	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T133	2		T134	2		T193	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T134	1		T190	1		T194	2
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T132	1		T133	1		T134	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T132	3		T133	1		T134	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T192	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T134	1		T195	1		T190	3