Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	578552030	55204	0	0
RunThenComplete_M	578552030	740787	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	55204	0	0
T1	2466	3	0	0
T2	6031	3	0	0
T3	17726	3	0	0
T4	160720	43	0	0
T8	39865	7	0	0
T9	6168	0	0	0
T18	15599	5	0	0
T38	81290	73	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	125	0	0
T47	0	92	0	0
T57	0	100	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	740787	0	0
T1	2466	10	0	0
T2	6031	10	0	0
T3	17726	9	0	0
T4	160720	204	0	0
T8	39865	46	0	0
T9	6168	1	0	0
T18	15599	19	0	0
T38	81290	74	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	309	0	0
T57	0	235	0	0