Unified Coverage Report :: Module :: prim_subreg

Module : prim_subreg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state_fifo_empty	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_entropy_refresh_hash_cnt	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state_kmac_done	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_kmac_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_kmac_done	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_kmac_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_mode.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_mode.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_mode.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_entropy_period_prescaler	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_entropy_period_wait_timer	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_len	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_prefix_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_err_code	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 + DW=32,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_prefix_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_err_code

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_mode.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_mode.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_mode.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_mode.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_mode.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_mode.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL,Mubi=0 + DW=10,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_entropy_period_prescaler

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.committed_reg

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_entropy_refresh_hash_cnt

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_entropy_period_wait_timer

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_kstrength.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_kstrength.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_kstrength.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_len

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_kmac_done

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_kmac_err

SCORE	COND
65.24	50.00

tb.dut.u_reg.u_intr_state_fifo_empty

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_kmac_done

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_fifo_empty

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_kmac_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_kmac_en.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_kmac_en.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_kmac_en.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_msg_endianness.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_msg_endianness.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_msg_endianness.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_state_endianness.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_state_endianness.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_state_endianness.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_sideload.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_sideload.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_sideload.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_msg_mask.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_msg_mask.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_msg_mask.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_ready.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_ready.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_entropy_ready.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3