Unified Coverage Report :: Module Instance :: tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.43	98.55	77.78			80.77	84.62	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.78	78.57	38.46			71.43	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.53	86.11	54.84			62.50	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.43	98.55	77.78			80.77	84.62	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	71.04	90.91	66.67			55.56

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.94	92.31	47.06			85.71	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.00	91.43	57.14			68.75	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.43	98.55	77.78			80.77	84.62	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	71.04	90.91	66.67			55.56

Module Instance : tb.dut.u_msgfifo.u_msgfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.72	100.00	93.62	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.56	98.61	83.33			92.31	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.56	98.61	83.33			92.31	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.56	98.61	83.33			92.31	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T9 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T9 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T9 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T9,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T9

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578552030	45571920	0	0
DataKnown_AKnownEnable	578552030	578396025	0	0
DepthKnown_A	578552030	578396025	0	0
RvalidKnown_A	578552030	578396025	0	0
WreadyKnown_A	578552030	578396025	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578552030	45571920	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	45571920	0	0
T1	2466	75	0	0
T2	6031	73	0	0
T3	17726	0	0	0
T4	160720	0	0	0
T8	39865	528	0	0
T9	6168	62	0	0
T10	0	1961	0	0
T18	15599	621	0	0
T38	81290	820	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	752	0	0
T47	0	2681	0	0
T57	0	643	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	45571920	0	0
T1	2466	75	0	0
T2	6031	73	0	0
T3	17726	0	0	0
T4	160720	0	0	0
T8	39865	528	0	0
T9	6168	62	0	0
T10	0	1961	0	0
T18	15599	621	0	0
T38	81290	820	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	752	0	0
T47	0	2681	0	0
T57	0	643	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	11	78.57
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        unreachable      assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        0/1     ==>            storage[0] <= wdata_i;
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        0/1     ==>        assign rdata_int = storage_rdata;
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	4	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	4	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578552030	0	0	0
DataKnown_AKnownEnable	578552030	578396025	0	0
DepthKnown_A	578552030	578396025	0	0
RvalidKnown_A	578552030	578396025	0	0
WreadyKnown_A	578552030	578396025	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578552030	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	0	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	0	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        unreachable      assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        unreachable            storage[0] <= wdata_i;
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Covered	Percent
Conditions	17	8	47.06
Logical	17	8	47.06
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	1	1	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==> (Unreachable)  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==> (Unreachable)
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	4	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	4	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578552030	0	0	0
DataKnown_AKnownEnable	578552030	578396025	0	0
DepthKnown_A	578552030	578396025	0	0
RvalidKnown_A	578552030	578396025	0	0
WreadyKnown_A	578552030	578396025	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578552030	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	0	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	0	0	0

Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T9 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T4,T45
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (72'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T9

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578274493	58075092	0	0
DataKnown_AKnownEnable	578552030	578396025	0	0
DepthKnown_A	578552030	578396025	0	0
RvalidKnown_A	578552030	578396025	0	0
WreadyKnown_A	578552030	578396025	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578274493	58075092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578274493	58075092	0	0
T1	2466	734	0	0
T2	6031	456	0	0
T3	17726	0	0	0
T4	160720	16202	0	0
T8	39865	3066	0	0
T9	6168	4720	0	0
T18	15599	1450	0	0
T38	81290	360	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	12524	0	0
T47	0	7019	0	0
T57	0	14135	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	578274493	58075092	0	0
T1	2466	734	0	0
T2	6031	456	0	0
T3	17726	0	0	0
T4	160720	16202	0	0
T8	39865	3066	0	0
T9	6168	4720	0	0
T18	15599	1450	0	0
T38	81290	360	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	12524	0	0
T47	0	7019	0	0
T57	0	14135	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T9 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T9 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T9 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T9,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T9

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578552030	23453584	0	0
DataKnown_AKnownEnable	578552030	578396025	0	0
DepthKnown_A	578552030	578396025	0	0
RvalidKnown_A	578552030	578396025	0	0
WreadyKnown_A	578552030	578396025	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578552030	23453584	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	23453584	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	25437	0	0
T8	39865	724	0	0
T9	6168	396	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	23453584	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	25437	0	0
T8	39865	724	0	0
T9	6168	396	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T9 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T9 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T9 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T9

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578552030	12627480	0	0
DataKnown_AKnownEnable	578552030	578396025	0	0
DepthKnown_A	578552030	578396025	0	0
RvalidKnown_A	578552030	578396025	0	0
WreadyKnown_A	578552030	578396025	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578552030	12627480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	12627480	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	5676	0	0
T8	39865	724	0	0
T9	6168	84	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	12627480	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	5676	0	0
T8	39865	724	0	0
T9	6168	84	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T9 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T9 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T9,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T47
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T9

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578552030	23413029	0	0
DataKnown_AKnownEnable	578552030	578396025	0	0
DepthKnown_A	578552030	578396025	0	0
RvalidKnown_A	578552030	578396025	0	0
WreadyKnown_A	578552030	578396025	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578552030	23413029	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	23413029	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	25437	0	0
T8	39865	724	0	0
T9	6168	396	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	578396025	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	578552030	23413029	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	25437	0	0
T8	39865	724	0	0
T9	6168	396	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579897769	114238255	0	0
DataKnown_AKnownEnable	579897769	579689774	0	0
DepthKnown_A	579897769	579689774	0	0
RvalidKnown_A	579897769	579689774	0	0
WreadyKnown_A	579897769	579689774	0	0
gen_passthru_fifo.paramCheckPass	887	887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	114238255	0	0
T1	2466	554	0	0
T2	6031	532	0	0
T3	17726	210	0	0
T4	160720	7972	0	0
T8	39865	4458	0	0
T9	6168	231	0	0
T18	15599	5013	0	0
T38	81290	6839	0	0
T39	1993	156	0	0
T40	1068	22	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	887	887	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579897769	173365256	0	0
DataKnown_AKnownEnable	579897769	579689774	0	0
DepthKnown_A	579897769	579689774	0	0
RvalidKnown_A	579897769	579689774	0	0
WreadyKnown_A	579897769	579689774	0	0
gen_passthru_fifo.paramCheckPass	887	887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	173365256	0	0
T1	2466	554	0	0
T2	6031	532	0	0
T3	17726	934	0	0
T4	160720	35520	0	0
T8	39865	3410	0	0
T9	6168	1125	0	0
T18	15599	4847	0	0
T38	81290	6839	0	0
T39	1993	156	0	0
T40	1068	22	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	887	887	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579897769	12723693	0	0
DataKnown_AKnownEnable	579897769	579689774	0	0
DepthKnown_A	579897769	579689774	0	0
RvalidKnown_A	579897769	579689774	0	0
WreadyKnown_A	579897769	579689774	0	0
gen_passthru_fifo.paramCheckPass	887	887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	12723693	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	5676	0	0
T8	39865	724	0	0
T9	6168	84	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	887	887	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579897769	23471169	0	0
DataKnown_AKnownEnable	579897769	579689774	0	0
DepthKnown_A	579897769	579689774	0	0
RvalidKnown_A	579897769	579689774	0	0
WreadyKnown_A	579897769	579689774	0	0
gen_passthru_fifo.paramCheckPass	887	887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	23471169	0	0
T1	2466	48	0	0
T2	6031	48	0	0
T3	17726	0	0	0
T4	160720	25437	0	0
T8	39865	724	0	0
T9	6168	396	0	0
T10	0	10200	0	0
T18	15599	1268	0	0
T38	81290	2336	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	9120	0	0
T57	0	7298	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	887	887	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579897769	28408172	0	0
DataKnown_AKnownEnable	579897769	579689774	0	0
DepthKnown_A	579897769	579689774	0	0
RvalidKnown_A	579897769	579689774	0	0
WreadyKnown_A	579897769	579689774	0	0
gen_passthru_fifo.paramCheckPass	887	887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	28408172	0	0
T1	2466	75	0	0
T2	6031	73	0	0
T3	17726	0	0	0
T4	160720	0	0	0
T8	39865	528	0	0
T9	6168	14	0	0
T10	0	2814	0	0
T18	15599	621	0	0
T38	81290	820	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	752	0	0
T47	0	588	0	0
T57	0	643	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	887	887	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579897769	45605423	0	0
DataKnown_AKnownEnable	579897769	579689774	0	0
DepthKnown_A	579897769	579689774	0	0
RvalidKnown_A	579897769	579689774	0	0
WreadyKnown_A	579897769	579689774	0	0
gen_passthru_fifo.paramCheckPass	887	887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	45605423	0	0
T1	2466	75	0	0
T2	6031	73	0	0
T3	17726	0	0	0
T4	160720	0	0	0
T8	39865	528	0	0
T9	6168	62	0	0
T10	0	1961	0	0
T18	15599	621	0	0
T38	81290	820	0	0
T39	1993	0	0	0
T40	1068	0	0	0
T41	0	752	0	0
T47	0	2681	0	0
T57	0	643	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	579689774	0	0
T1	2466	2379	0	0
T2	6031	5933	0	0
T3	17726	17676	0	0
T4	160720	160658	0	0
T8	39865	39771	0	0
T9	6168	6036	0	0
T18	15599	15503	0	0
T38	81290	81206	0	0
T39	1993	1909	0	0
T40	1068	971	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	887	887	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0