Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	579897769	18888	0	0
entropy_period_rd_A	579897769	1305	0	0
intr_enable_rd_A	579897769	2380	0	0
prefix_0_rd_A	579897769	1649	0	0
prefix_10_rd_A	579897769	1506	0	0
prefix_1_rd_A	579897769	1589	0	0
prefix_2_rd_A	579897769	1698	0	0
prefix_3_rd_A	579897769	1638	0	0
prefix_4_rd_A	579897769	1608	0	0
prefix_5_rd_A	579897769	1607	0	0
prefix_6_rd_A	579897769	1526	0	0
prefix_7_rd_A	579897769	1676	0	0
prefix_8_rd_A	579897769	1547	0	0
prefix_9_rd_A	579897769	1594	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	18888	0	0
T5	800694	0	0	0
T12	97923	1388	0	0
T13	787796	0	0	0
T14	63251	0	0	0
T15	246192	0	0	0
T26	0	1074	0	0
T28	0	407	0	0
T29	0	7804	0	0
T42	53510	0	0	0
T85	0	2071	0	0
T132	0	1	0	0
T140	0	1709	0	0
T141	0	978	0	0
T142	0	472	0	0
T143	0	4	0	0
T144	4537	0	0	0
T145	5836	0	0	0
T146	163354	0	0	0
T147	198587	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1305	0	0
T28	245920	14	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	10	0	0
T109	0	33	0	0
T114	0	73	0	0
T119	0	26	0	0
T161	0	11	0	0
T162	0	11	0	0
T163	0	5	0	0
T164	0	220	0	0
T165	0	29	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	2380	0	0
T28	245920	19	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	16	0	0
T109	0	18	0	0
T119	0	35	0	0
T138	0	17	0	0
T161	0	10	0	0
T162	0	35	0	0
T163	0	11	0	0
T164	0	479	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0
T172	0	11	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1649	0	0
T28	245920	17	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T109	0	30	0	0
T114	0	59	0	0
T119	0	33	0	0
T161	0	4	0	0
T162	0	14	0	0
T163	0	5	0	0
T164	0	466	0	0
T165	0	9	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0
T173	0	9	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1506	0	0
T28	245920	22	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	15	0	0
T109	0	15	0	0
T114	0	61	0	0
T119	0	31	0	0
T161	0	5	0	0
T162	0	34	0	0
T164	0	382	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0
T173	0	8	0	0
T174	0	216	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1589	0	0
T28	245920	30	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	12	0	0
T109	0	23	0	0
T114	0	55	0	0
T119	0	22	0	0
T142	0	2	0	0
T162	0	59	0	0
T163	0	32	0	0
T164	0	436	0	0
T165	0	14	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1698	0	0
T28	245920	16	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	9	0	0
T109	0	23	0	0
T114	0	53	0	0
T119	0	23	0	0
T161	0	8	0	0
T162	0	50	0	0
T163	0	12	0	0
T164	0	510	0	0
T165	0	23	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1638	0	0
T28	245920	30	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	14	0	0
T109	0	19	0	0
T114	0	51	0	0
T119	0	20	0	0
T161	0	3	0	0
T162	0	21	0	0
T164	0	440	0	0
T165	0	37	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0
T173	0	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1608	0	0
T28	245920	17	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	11	0	0
T109	0	11	0	0
T114	0	46	0	0
T119	0	31	0	0
T161	0	2	0	0
T162	0	38	0	0
T163	0	32	0	0
T164	0	482	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0
T173	0	6	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1607	0	0
T28	245920	23	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	11	0	0
T109	0	18	0	0
T114	0	55	0	0
T119	0	30	0	0
T161	0	10	0	0
T162	0	19	0	0
T163	0	2	0	0
T164	0	446	0	0
T165	0	44	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1526	0	0
T28	245920	23	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	3	0	0
T109	0	22	0	0
T114	0	58	0	0
T119	0	20	0	0
T161	0	4	0	0
T162	0	7	0	0
T163	0	22	0	0
T164	0	436	0	0
T165	0	17	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1676	0	0
T28	245920	24	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	14	0	0
T109	0	12	0	0
T114	0	64	0	0
T119	0	21	0	0
T161	0	6	0	0
T162	0	23	0	0
T163	0	19	0	0
T164	0	523	0	0
T165	0	7	0	0
T166	135582	0	0	0
T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1547	0	0
T28	245920	22	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	7	0	0
T109	0	6	0	0
T114	0	54	0	0
T119	0	20	0	0
T162	0	58	0	0
T163	0	15	0	0
T164	0	437	0	0
T165	0	6	0	0
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T167	108534	0	0	0
T168	283497	0	0	0
T169	31968	0	0	0
T170	154512	0	0	0
T171	274348	0	0	0
T175	0	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579897769	1594	0	0
T28	245920	13	0	0
T29	522727	0	0	0
T50	3655	0	0	0
T76	2426	0	0	0
T106	0	5	0	0
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T114	0	55	0	0
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T165	0	39	0	0
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T167	108534	0	0	0
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T169	31968	0	0	0
T170	154512	0	0	0
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T173	0	11	0	0