Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15892901	1			T1	2		T2	134		T3	71
all_values[1]	15892901	1			T1	2		T2	134		T3	71
all_values[2]	15892901	1			T1	2		T2	134		T3	71

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

474330

1

T2

140

T3

24

T14

81

auto[1]

47204373

1

T1

6

T2

262

T3

189

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47457657

1

T1

3

T2

387

T3

198

auto[1]

221046

1

T1

3

T2

15

T3

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	122549	1			T2	4		T3	11		T46	1
all_values[0]	auto[0]	auto[1]	1223	1			T2	2		T3	4		T46	2
all_values[0]	auto[1]	auto[0]	15696670	1			T1	1		T2	125		T3	55
all_values[0]	auto[1]	auto[1]	72459	1			T1	1		T2	3		T3	1
all_values[1]	auto[0]	auto[0]	171023	1			T2	129		T3	7		T46	1
all_values[1]	auto[0]	auto[1]	1029	1			T2	5		T3	2		T46	2
all_values[1]	auto[1]	auto[0]	15648196	1			T1	1		T3	59		T14	659
all_values[1]	auto[1]	auto[1]	72653	1			T1	1		T3	3		T14	7
all_values[2]	auto[0]	auto[0]	177511	1			T14	80		T50	5		T4	2
all_values[2]	auto[0]	auto[1]	995	1			T14	1		T50	1		T67	5
all_values[2]	auto[1]	auto[0]	15641708	1			T1	1		T2	129		T3	66
all_values[2]	auto[1]	auto[1]	72687	1			T1	1		T2	5		T3	5