Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 0 3 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 0 18 100.00 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 51028 1 T1 8 T2 2 T3 2
auto[1] 62122 1 T2 4 T3 4 T14 12



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 28117 1 T1 4 T2 3 T3 2
lower_val 28162 1 T1 2 T14 8 T46 48
zero_val 974 1 T1 1 T2 1 T3 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for wait_timer_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 40948 1 T1 4 T2 4 T3 2
lower_val 41196 1 T1 4 T3 2 T14 4
zero_val 31006 1 T2 2 T3 2 T14 6



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for entropy_timer_cross

Bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 6183 1 T1 1 T2 1 T46 21
higher_val higher_val auto[1] 3926 1 T2 1 T4 19 T64 21
higher_val lower_val auto[0] 6314 1 T1 3 T46 27 T31 6
higher_val lower_val auto[1] 3955 1 T3 1 T14 1 T4 12
higher_val zero_val auto[0] 58 1 T24 1 T180 1 T195 1
higher_val zero_val auto[1] 7681 1 T2 1 T3 1 T4 23
lower_val higher_val auto[0] 6243 1 T1 1 T46 25 T31 9
lower_val higher_val auto[1] 3909 1 T14 2 T4 17 T64 22
lower_val lower_val auto[0] 6217 1 T1 1 T14 1 T46 23
lower_val lower_val auto[1] 3921 1 T14 1 T4 24 T64 22
lower_val zero_val auto[0] 64 1 T55 1 T196 1 T24 2
lower_val zero_val auto[1] 7808 1 T14 4 T4 46 T64 34
zero_val higher_val auto[0] 295 1 T1 1 T2 1 T3 1
zero_val higher_val auto[1] 72 1 T33 1 T93 1 T197 1
zero_val lower_val auto[0] 280 1 T14 1 T46 1 T31 1
zero_val lower_val auto[1] 71 1 T34 1 T197 1 T24 2
zero_val zero_val auto[0] 178 1 T49 1 T64 1 T55 1
zero_val zero_val auto[1] 78 1 T67 2 T29 3 T33 1

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