SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 20 | 0 | 20 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
hash_mode | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
kmac_mode | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
msgfifo_depth | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 | |
msgfifo_empty | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
msgfifo_full | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
cshake | 14439111 | 1 | T1 | 4 | T2 | 171 | T3 | 102 | ||||
shake | 6563281 | 1 | T14 | 76 | T31 | 16 | T4 | 49 | ||||
sha3 | 1757017 | 1 | T14 | 217 | T46 | 1697 | T31 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 8319102 | 1 | T14 | 293 | T46 | 1697 | T31 | 22 | ||||
auto[1] | 14440307 | 1 | T1 | 4 | T2 | 171 | T3 | 102 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
invalid | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
depth[0x00] | 17462244 | 1 | T1 | 4 | T2 | 62 | T3 | 36 | ||||
depth[0x01] | 830524 | 1 | T2 | 9 | T3 | 4 | T14 | 5 | ||||
depth[0x02] | 849097 | 1 | T2 | 11 | T3 | 4 | T14 | 1 | ||||
depth[0x03] | 784116 | 1 | T2 | 11 | T3 | 4 | T49 | 2 | ||||
depth[0x04] | 660096 | 1 | T2 | 8 | T3 | 5 | T64 | 37 | ||||
depth[0x05] | 495273 | 1 | T2 | 7 | T3 | 2 | T51 | 130 | ||||
depth[0x06] | 340367 | 1 | T2 | 4 | T3 | 2 | T51 | 50 | ||||
depth[0x07] | 275709 | 1 | T2 | 4 | T3 | 2 | T51 | 47 | ||||
depth[0x08] | 269568 | 1 | T2 | 7 | T3 | 3 | T51 | 66 | ||||
depth[0x09] | 254626 | 1 | T2 | 4 | T3 | 2 | T51 | 52 | ||||
depth[0x0a] | 537789 | 1 | T2 | 44 | T3 | 38 | T51 | 496 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5297165 | 1 | T2 | 109 | T3 | 66 | T14 | 6 | ||||
auto[1] | 17462244 | 1 | T1 | 4 | T2 | 62 | T3 | 36 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22221620 | 1 | T1 | 4 | T2 | 127 | T3 | 64 | ||||
auto[1] | 537789 | 1 | T2 | 44 | T3 | 38 | T51 | 496 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |